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* hw/riscv: Fix OT IBEX reset vectorAlexander Wagner2021-05-111-1/+1
* hw/riscv: Enable VIRTIO_VGA for RISC-V virt machineAlistair Francis2021-05-111-0/+1
* hw/opentitan: Update the interrupt layoutAlistair Francis2021-05-111-4/+4
* hw/riscv: Connect Shakti UART to Shakti platformVijai Kumar K2021-05-111-0/+8
* riscv: Add initial support for Shakti C machineVijai Kumar K2021-05-113-0/+184
* hw/riscv: sifive_e: Add 'const' to sifive_e_memmap[]Bin Meng2021-05-111-1/+1
* Do not include exec/address-spaces.h if it's not really necessaryThomas Huth2021-05-022-2/+0Star
* hw: Do not include qemu/log.h if it is not necessaryThomas Huth2021-05-026-6/+0Star
* hw: Do not include hw/irq.h if it is not necessaryThomas Huth2021-05-021-1/+0Star
* hw/riscv: microchip_pfsoc: Map EMMC/SD mux registerBin Meng2021-03-231-0/+6
* hw/riscv: allow ramfb on virtAsherah Connor2021-03-231-0/+3
* hw/riscv: Add fw_cfg support to virtAsherah Connor2021-03-232-0/+31
* Merge remote-tracking branch 'remotes/stsquad/tags/pull-testing-docs-xen-upda...Peter Maydell2021-03-111-10/+10
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| * hw/riscv: migrate fdt field to generic MachineStateAlex Bennée2021-03-101-10/+10
* | qtest: delete superfluous inclusions of qtest.hChen Qun2021-03-091-1/+0Star
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* hw/riscv: virt: Map high mmio for PCIeBin Meng2021-03-041-2/+33
* hw/riscv: virt: Limit RAM size in a 32-bit systemBin Meng2021-03-041-0/+10
* hw/riscv: virt: Drop the 'link_up' parameter of gpex_pcie_init()Bin Meng2021-03-041-7/+7
* hw/riscv: Drop 'struct MemmapEntry'Bin Meng2021-03-046-37/+19Star
* hw/riscv: sifive_u: Add QSPI2 controller and connect an SD cardBin Meng2021-03-042-2/+42
* hw/riscv: sifive_u: Add QSPI0 controller and connect a flashBin Meng2021-03-042-0/+54
* riscv: Pass RISCVHartArrayState by pointerAlistair Francis2021-01-164-19/+17Star
* hw/riscv: sifive_u: Use SIFIVE_U_CPU for mc->default_cpu_typeBin Meng2021-01-161-5/+1Star
* RISC-V: Place DTB at 3GB boundary instead of 4GBAtish Patra2021-01-161-4/+4
* riscv/opentitan: Update the OpenTitan memory layoutAlistair Francis2020-12-181-24/+57
* hw/riscv: Use the CPU to determine if 32-bitAlistair Francis2020-12-184-34/+24Star
* hw/riscv: sifive_u: Remove compile time XLEN checksAlistair Francis2020-12-181-25/+30
* hw/riscv: spike: Remove compile time XLEN checksAlistair Francis2020-12-181-21/+24
* hw/riscv: virt: Remove compile time XLEN checksAlistair Francis2020-12-181-15/+17
* hw/riscv: boot: Remove compile time XLEN checksAlistair Francis2020-12-184-28/+34
* riscv: virt: Remove target macro conditionalsAlistair Francis2020-12-181-1/+1
* riscv: spike: Remove target macro conditionalsAlistair Francis2020-12-181-1/+1
* hw/riscv: Expand the is 32-bit check to support more CPUsAlistair Francis2020-12-181-1/+11
* hw/riscv: microchip_pfsoc: add QSPI NOR flashVitaly Wool2020-12-181-0/+21
* hw/riscv: sifive_u: Add UART1 DT node in the generated DTBAnup Patel2020-12-181-0/+15
* vl: make qemu_get_machine_opts staticPaolo Bonzini2020-12-152-8/+4Star
* vl: extract softmmu/datadir.cPaolo Bonzini2020-12-101-0/+1
* riscv: do not use ram_size globalPaolo Bonzini2020-12-101-2/+3
* hw/riscv: microchip_pfsoc: Hook the I2C1 controllerBin Meng2020-11-031-0/+6
* hw/riscv: microchip_pfsoc: Correct DDR memory mapBin Meng2020-11-031-6/+44
* hw/riscv: microchip_pfsoc: Map the reserved memory at address 0Bin Meng2020-11-031-1/+10
* hw/riscv: microchip_pfsoc: Connect the SYSREG moduleBin Meng2020-11-032-3/+7
* hw/riscv: microchip_pfsoc: Connect the IOSCB moduleBin Meng2020-11-032-5/+9
* hw/riscv: microchip_pfsoc: Connect DDR memory controller modulesBin Meng2020-11-032-0/+19
* hw/riscv: microchip_pfsoc: Document where to look at the SoC memory mapsBin Meng2020-11-031-0/+18
* hw/riscv: virt: Allow passing custom DTBAnup Patel2020-11-031-7/+20
* hw/riscv: sifive_u: Allow passing custom DTBAnup Patel2020-11-031-8/+20
* hw/riscv: Load the kernel after the firmwareAlistair Francis2020-10-226-15/+42
* hw/riscv: Add a riscv_is_32_bit() functionAlistair Francis2020-10-221-0/+9
* hw/riscv: Return the end address of the loaded firmwareAlistair Francis2020-10-221-11/+17
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