summaryrefslogtreecommitdiffstats
path: root/hw/riscv
Commit message (Expand)AuthorAgeFilesLines
* riscv: Initial commit of OpenTitan machineAlistair Francis2020-06-033-0/+190
* riscv: sifive_e: Manually define the machineAlistair Francis2020-06-031-11/+30
* hw/riscv: spike: Remove deprecated ISA specific machinesAlistair Francis2020-06-031-217/+0Star
* hw/riscv: virt: Remove the riscv_ prefix of the machine* functionsBin Meng2020-06-031-10/+10
* hw/riscv: sifive_u: Remove the riscv_ prefix of the soc* functionsBin Meng2020-06-031-12/+12
* riscv: Change the default behavior if no -bios option is specifiedBin Meng2020-06-031-27/+4Star
* riscv: Suppress the error report for QEMU testing with riscv_find_firmware()Bin Meng2020-06-031-3/+11
* hw: Use QEMU_IS_ALIGNED() on parallel flash block sizePhilippe Mathieu-Daudé2020-05-181-1/+1
* qom: Drop parameter @errp of object_property_add() & friendsMarkus Armbruster2020-05-152-7/+8
* qom: Drop object_property_set_description() parameter @errpMarkus Armbruster2020-05-151-3/+2Star
* hw/riscv/spike: Allow more than one CPUsAnup Patel2020-04-291-1/+1
* hw/riscv/spike: Allow loading firmware separately using -bios optionAnup Patel2020-04-291-1/+23
* hw/riscv: Add optional symbol callback ptr to riscv_load_firmware()Anup Patel2020-04-293-7/+10
* riscv: sifive_e: Support changing CPU typeCorey Wharton2020-04-291-2/+3
* hw/riscv: Generate correct "mmu-type" for 32-bit machinesBin Meng2020-04-293-0/+12
* riscv/sifive_u: Add a serial property to the sifive_u machineBin Meng2020-04-291-0/+20
* riscv/sifive_u: Add a serial property to the sifive_u SoCAlistair Francis2020-04-291-1/+7
* riscv/sifive_u: Fix up file orderingAlistair Francis2020-04-291-54/+54
* various: Remove suspicious '\' character outside of #define in C codePhilippe Mathieu-Daudé2020-04-291-1/+1
* Merge remote-tracking branch 'remotes/bonzini/tags/for-upstream' into stagingPeter Maydell2020-03-172-6/+5Star
|\
| * hw/riscv: Let devices own the MemoryRegion they createPhilippe Mathieu-Daudé2020-03-172-4/+4
| * hw/riscv: Use memory_region_init_rom() with read-only regionsPhilippe Mathieu-Daudé2020-03-171-3/+2Star
* | riscv: sifive_u: Update BIOS_FILENAME for 32-bitBin Meng2020-03-171-1/+5
|/
* Merge remote-tracking branch 'remotes/palmer/tags/riscv-for-master-5.0-sf3' i...Peter Maydell2020-03-035-7/+15
|\
| * hw/riscv: Provide rdtime callback for TCG in CLINT emulationAnup Patel2020-02-275-7/+14
| * riscv: virt: Allow PCI address 0Bin Meng2020-02-271-0/+1
* | hw: Make MachineClass::is_default a boolean typePhilippe Mathieu-Daudé2020-02-281-1/+1
|/
* riscv: virt: Use Goldfish RTC deviceAnup Patel2020-02-102-0/+17
* riscv/virt: Add syscon reboot and poweroff DT nodesAnup Patel2020-02-101-4/+22
* hw/core/loader: Let load_elf() populate a field with CPU-specific flagsAleksandar Markovic2020-01-291-2/+2
* Merge remote-tracking branch 'remotes/bonzini/tags/for-upstream' into stagingPeter Maydell2020-01-274-4/+4
|\
| * qdev: set properties with device_class_set_props()Marc-André Lureau2020-01-244-4/+4
* | riscv/sifive_u: fix a memory leak in soc_realize()Pan Nengyuan2020-01-161-0/+1
|/
* chardev: Use QEMUChrEvent enum in IOEventHandler typedefPhilippe Mathieu-Daudé2020-01-082-2/+2
* hw/riscv: Add optional symbol callback ptr to riscv_load_kernel()Zhuang, Siwei (Data61, Kensington NSW)2019-11-255-9/+12
* RISC-V: virt: This is a "sifive,test1" test finisherPalmer Dabbelt2019-11-251-1/+4
* riscv/virt: Increase flash sizeAlistair Francis2019-11-141-1/+1
* riscv/boot: Fix possible memory leakAlistair Francis2019-10-281-7/+4Star
* riscv/virt: Jump to pflash if specifiedAlistair Francis2019-10-281-1/+10
* riscv/virt: Add the PFlash CFI01 deviceAlistair Francis2019-10-282-0/+87
* riscv/virt: Manually define the machineAlistair Francis2019-10-281-6/+24
* riscv/sifive_u: Add the start-in-flash propertyAlistair Francis2019-10-281-1/+29
* riscv/sifive_u: Manually define the machineAlistair Francis2019-10-281-13/+31
* riscv/sifive_u: Add QSPI memory regionAlistair Francis2019-10-281-0/+8
* riscv/sifive_u: Add L2-LIM cache memoryAlistair Francis2019-10-281-0/+16
* riscv: sifive_u: Add ethernet0 to the aliases nodeBin Meng2019-10-281-1/+4
* riscv: hw: Drop "clock-frequency" property of cpu nodesBin Meng2019-10-283-6/+0Star
* riscv: sifive_u: Update model and compatible strings in device treeBin Meng2019-09-171-2/+3
* riscv: sifive_u: Remove handcrafted clock nodes for UART and ethernetBin Meng2019-09-171-23/+1Star
* riscv: sifive_u: Fix broken GEM supportBin Meng2019-09-172-4/+21
generated by cgit v1.2.3-55-g7522 (git 2.39.0) at 2025-01-08 17:55:36 +0100