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* aspeed/smc: Cache AspeedSMCClassCédric Le Goater2022-10-241-5/+4Star
* ssi: cache SSIPeripheralClass to avoid GET_CLASS()Alex Bennée2022-10-241-10/+8Star
* hw/ssi: ibex_spi: fixup/add rw1c functionalityWilfred Mallawa2022-10-141-3/+33
* hw/ssi: ibex_spi: fixup coverity issueWilfred Mallawa2022-10-141-64/+68
* hw/ssi: ibex_spi: update reg addrWilfred Mallawa2022-09-261-1/+1
* hw/ssi: ibex_spi: fixup typos in ibex_spi_hostWilfred Mallawa2022-09-261-3/+3
* aspeed/smc: Fix potential overflowCédric Le Goater2022-06-301-2/+2
* aspeed/smc: Add AST1030 supportSteven Lee2022-05-021-0/+157
* hw/ssi: Add Ibex SPI device modelWilfred Mallawa2022-04-223-0/+620
* aspeed/smc: Fix error logCédric Le Goater2022-03-081-1/+1
* aspeed/smc: Let the SSI core layer define the bus nameCédric Le Goater2022-03-081-1/+1
* aspeed/smc: Rename 'max_peripherals' to 'cs_num_max'Cédric Le Goater2022-03-081-21/+21
* aspeed/smc: Remove 'num_cs' fieldCédric Le Goater2022-03-081-7/+0Star
* aspeed/smc: Use max number of CE instead of 'num_cs'Cédric Le Goater2022-03-081-4/+4
* migration: Remove load_state_old and minimum_version_id_oldPeter Maydell2022-03-021-1/+0Star
* aspeed/smc: Add an address mask on segment registersCédric Le Goater2022-02-261-0/+11
* hw/ssi: Add a model of Xilinx Versal's OSPI flash memory controllerFrancisco Iglesias2022-01-282-0/+1854
* aspeed/smc: Use a container for the flash mmio address spaceCédric Le Goater2021-10-221-4/+7
* aspeed/smc: Dump address offset in trace eventsCédric Le Goater2021-10-121-3/+3
* aspeed/smc: Introduce a new addr_width() class handlerCédric Le Goater2021-10-121-7/+12
* aspeed/smc: Add default reset valuesCédric Le Goater2021-10-121-25/+27
* aspeed/smc: QOMify AspeedSMCFlashCédric Le Goater2021-10-121-8/+68
* aspeed/smc: Rename AspeedSMCFlash 'id' to 'cs'Cédric Le Goater2021-10-121-15/+15
* aspeed/smc: Remove the 'size' attribute from AspeedSMCFlashCédric Le Goater2021-10-121-3/+2Star
* aspeed/smc: Drop AspeedSMCController structureCédric Le Goater2021-10-121-383/+478
* aspeed/smc: Stop using the model name for the memory regionsCédric Le Goater2021-10-121-15/+10Star
* aspeed/smc: Introduce aspeed_smc_error() helperCédric Le Goater2021-10-121-52/+45Star
* aspeed/smc: Add watchdog Control/Status RegistersCédric Le Goater2021-10-121-1/+18
* qbus: Rename qbus_create() to qbus_new()Peter Maydell2021-09-301-1/+1
* Merge remote-tracking branch 'remotes/vivier2/tags/trivial-branch-for-6.1-pul...Peter Maydell2021-05-053-3/+0Star
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| * Do not include exec/address-spaces.h if it's not really necessaryThomas Huth2021-05-021-1/+0Star
| * Do not include sysemu/sysemu.h if it's not really necessaryThomas Huth2021-05-021-1/+0Star
| * hw: Do not include qemu/log.h if it is not necessaryThomas Huth2021-05-021-1/+0Star
* | aspeed/smc: Add extra controls to request DMACédric Le Goater2021-05-011-7/+67
* | aspeed/smc: Add a 'features' attribute to the object classCédric Le Goater2021-05-011-19/+25
* | hw/arm/aspeed: Do not sysbus-map mmio flash region directly, use aliasPhilippe Mathieu-Daudé2021-05-011-3/+4
* | aspeed/smc: Remove unused "sdram-base" propertyCédric Le Goater2021-05-011-1/+0Star
* | aspeed/smc: Use the RAM memory region for DMAsCédric Le Goater2021-05-011-2/+1Star
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* hw/ssi: xilinx_spips: Remove DMA related dead codes from zynqmp_spipsXuzhou Cheng2021-03-101-10/+0Star
* hw/ssi: xilinx_spips: Clean up coding convention issuesXuzhou Cheng2021-03-101-9/+14
* hw/ssi: Add SiFive SPI controller supportBin Meng2021-03-043-0/+363
* hw/ssi: imx_spi: Correct tx and rx fifo endiannessBin Meng2021-02-021-5/+2Star
* hw/ssi: imx_spi: Correct the burst length > 32 bit transfer logicBin Meng2021-02-021-1/+1
* hw/ssi: imx_spi: Round up the burst length to be multiple of 8Bin Meng2021-02-021-1/+16
* hw/ssi: imx_spi: Disable chip selects when controller is disabledXuzhou Cheng2021-02-021-0/+6
* hw/ssi: imx_spi: Rework imx_spi_write() to handle block disabledPhilippe Mathieu-Daudé2021-02-021-4/+9
* hw/ssi: imx_spi: Rework imx_spi_read() to handle block disabledPhilippe Mathieu-Daudé2021-02-021-31/+29Star
* hw/ssi: imx_spi: Rework imx_spi_reset() to keep CONREG register valuePhilippe Mathieu-Daudé2021-02-021-8/+24
* hw/ssi: imx_spi: Remove pointless variable initializationPhilippe Mathieu-Daudé2021-02-021-2/+0Star
* hw/ssi: imx_spi: Remove imx_spi_update_irq() in imx_spi_reset()Bin Meng2021-02-021-4/+10
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