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* ssi: xilinx_spi: Initialise CS GPIOs as NULLPeter Crosthwaite2014-08-151-1/+1
| | | | | | | To properly indicate they are unconnected. Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
* ssi: Name the CS GPIOPeter Crosthwaite2014-05-281-2/+2
| | | | | | | | | | | | | | | To get it out of the default GPIO list. This allows child devices to use the un-named GPIO namespace without having to be SSI aware. That is, there is no more need for machines to know about the obscure policy where GPIO 0 is the SSI chip-select and GPIO 1..N are the concrete class GPIOs (defined locally as 0..N-1). This is most notable in stellaris, which uses a device which has both SSI and concrete level GPIOs. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Signed-off-by: Andreas Färber <afaerber@suse.de>
* savevm: Remove all the unneeded version_minimum_id_old (arm)Juan Quintela2014-05-134-6/+2Star
| | | | | | | | | | | | | | | | | | | | | After commit 767adce2d, they are redundant. This way we don't assign them except when needed. Once there, there were lots of cases where the ".fields" indentation was wrong: .fields = (VMStateField []) { and .fields = (VMStateField []) { Change all the combinations to: .fields = (VMStateField[]){ The biggest problem (apart from aesthetics) was that checkpatch complained when we copy&pasted the code from one place to another. Signed-off-by: Juan Quintela <quintela@redhat.com> [PMM: fixed minor conflict, corrected commit message typos] Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* pl022: fix buffer overun on invalid state loadMichael S. Tsirkin2014-05-051-0/+14
| | | | | | | | | | | | | CVE-2013-4530 pl022.c did not bounds check tx_fifo_head and rx_fifo_head after loading them from file and before they are used to dereference array. Reported-by: Michael S. Tsirkin <mst@redhat.com Reported-by: Anthony Liguori <anthony@codemonkey.ws> Signed-off-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Juan Quintela <quintela@redhat.com>
* ssi: Convert legacy SSI_BUS -> BUS castsPeter Crosthwaite2014-03-121-4/+5
| | | | | | | | | Remove two legacy ->qbus style casts from TYPE_SSI_BUS to TYPE_BUS in ssi.c. Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> [AF: Convert one missing ->qbus and rename parent field] Signed-off-by: Andreas Färber <afaerber@suse.de>
* ssi: Convert legacy SSI_SLAVE -> DEVICE castsPeter Crosthwaite2014-03-121-1/+1
| | | | | | | | Convert legacy ->qdev style casts from TYPE_SSI_SLAVE to TYPE_DEVICE. Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> [AF: Introduce local DeviceState variable for transition to QOM realize] Signed-off-by: Andreas Färber <afaerber@suse.de>
* hw/ssi/xilinx_spips.c: Avoid shifting left into sign bitPeter Maydell2014-03-101-2/+2
| | | | | | | | Add missing 'U' suffix to avoid shifting left into sign bit of a signed integer. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1392988008-15938-4-git-send-email-peter.maydell@linaro.org
* xilinx_spi: QOM cast cleanupAndreas Färber2013-07-291-11/+16
| | | | Signed-off-by: Andreas Färber <afaerber@suse.de>
* pl022: QOM cast cleanupAndreas Färber2013-07-291-8/+13
| | | | Signed-off-by: Andreas Färber <afaerber@suse.de>
* pl022: Rename pl022_state to PL022StateAndreas Färber2013-07-291-36/+36
| | | | Signed-off-by: Andreas Färber <afaerber@suse.de>
* hw/s*: pass owner to memory_region_init* functionsPaolo Bonzini2013-07-043-4/+6
| | | | Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
* memory: add owner argument to initialization functionsPaolo Bonzini2013-07-044-5/+5
| | | | Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
* qdev: Drop FROM_QBUS() macroAndreas Färber2013-06-071-1/+1
| | | | | | Use QOM cast macros I2C_BUS(), SSI_BUS(), PCI_BUS() instead. Signed-off-by: Andreas Färber <afaerber@suse.de>
* xilinx_spips: lqspi: Fix byte/misaligned accessPeter Crosthwaite2013-06-031-14/+17
| | | | | | | | | | | | The LQSPI bus attachment supports byte/halfword and misaligned accesses. Fixed. Refactored the LQSPI cache to be byte-wise instead of word wise accordingly. Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@gmail.com> Message-id: 5ec47b13563ad2d22105a1f26186d7756718394b.1369117359.git.peter.crosthwaite@xilinx.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* xilinx_spips: lqspi: Push more data to tx-fifoPeter Crosthwaite2013-06-031-4/+7
| | | | | | | | | | | | Do 16 words per fifo flush. Increases performance and decreases debug verbosity. This data depth has no real hardware analogue, so just go with something that has reasonable performance. Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@gmail.com> Message-id: 5621ee4621941d3639b5cacfdec26bd3148f31d5.1369117359.git.peter.crosthwaite@xilinx.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* xilinx_spips: Multiple debug verbosity levelsPeter Crosthwaite2013-06-031-28/+42
| | | | | | | | | | | The debug printfs on every SPI operation is extremely verbose. Add a second level of debug for this. Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@gmail.com> Message-id: f63478b8e5b29cc011cdc10e29f8537bb2fc2b5e.1369117359.git.peter.crosthwaite@xilinx.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* xilinx_spips: Debug msgs for Snoop statePeter Crosthwaite2013-06-031-0/+3
| | | | | | | | | | This is worth keeping track of when debugging the device model. Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@gmail.com> Message-id: d3b44ecf23d671798b062eee5dc362c716ea54cd.1369117359.git.peter.crosthwaite@xilinx.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* xilinx_spips: Fix striping behaviourPeter Crosthwaite2013-06-031-21/+63
| | | | | | | | | | | | | | The QSPI controller was using byte-wide stripes when striping across the two flashes in dual parallel mode. The real hardware however uses individual bit striping. QEMU misbehaves in the (corner) case where data is written/read in dual-parallel mode and read/written back in single mode. Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@gmail.com> Message-id: 718a61df1bf746ec06f6da44d12f8317af7b08ce.1369117359.git.peter.crosthwaite@xilinx.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* xilinx_spips: Fix CTRL register RW bitsPeter Crosthwaite2013-06-031-2/+3
| | | | | | | | | | | | The CTRL register was RAZ/WI on some of the RW bits. Even though the function behind these bits is invalid in QEMU, they should still be guest accessible. Fix. Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@gmail.com> Message-id: b7aaad93163ce4af0c428635804ac7b77a567b25.1369117359.git.peter.crosthwaite@xilinx.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* xilinx_spips: lqspi: Dont touch config registerPeter Crosthwaite2013-06-031-6/+6
| | | | | | | | | | | | | | The LQSPI mode is supposed to work via the automatic CS mode feature rather than manipulate CS lines itself. Now that auto CS is implemented remove LQSPIs CS mode override logic. There is still a need to manipulate the U_PAGE bit in LQSPI config register to implement dual-stack mode however. Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@gmail.com> Message-id: 000c8dd54df09523f17052638100722ef0f5a3af.1369117359.git.peter.crosthwaite@xilinx.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* xilinx_spips: Implement automatic CSPeter Crosthwaite2013-06-031-4/+14
| | | | | | | | | | | | Implement the automatic CS control feature. If the MANUAL_CS bit is cleared then the chip select stay de-asserted as long as the tx FIFO is empty. Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@gmail.com> Message-id: 1d67383adc42761af715a93f161344b9284dfc9a.1369117359.git.peter.crosthwaite@xilinx.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* xilinx_spips: Add automatic start supportPeter Crosthwaite2013-06-031-1/+2
| | | | | | | | | | | SPI has a mode where it automatically starts based on tx fifo occupancy. Implemented. Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@gmail.com> Message-id: f4e9accb5de87b526fff6ed937f63278db76533b.1369117359.git.peter.crosthwaite@xilinx.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* xilinx_spips: Trash LQ page cache on mode changePeter Crosthwaite2013-06-031-1/+24
| | | | | | | | | | | | | Invalidate the LQSPI cached page when transitioning into LQSPI mode. Otherwise there is a possibility that the controller will return stale data to the guest when transitioning back to LQ_MODE after a page program. Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@gmail.com> Message-id: 677490a6ee1953fe5d366e599d665de645ac84db.1369117359.git.peter.crosthwaite@xilinx.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* xilinx_spips: Fix QSPI FIFO sizePeter Crosthwaite2013-06-031-2/+25
| | | | | | | | | | | | | | | QSPI has a bigger FIFO than the regular SPI controller. Differentiate between the two with correct FIFO sizes for each. This is the first piece of class data for SPIPS, so this patch sees the creation of the XilinxSPIPSClass definition and assoicated QOM constructs. Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@gmail.com> Message-id: acee25dd5e203215cbc15ca5d3cb5d5b2efebe7b.1369117359.git.peter.crosthwaite@xilinx.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* xilinx_spips: Add verbose LQSPI debug outputPeter Crosthwaite2013-06-031-1/+4
| | | | | | | | | | You really need this is you want to track a guest banging on LQSPI. Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@gmail.com> Message-id: 26e508da4af11058d37daa777064c9e5c2a69abb.1369117359.git.peter.crosthwaite@xilinx.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* xilinx_spips: Inhibit interrupts in LQSPI modePeter Crosthwaite2013-06-031-1/+6
| | | | | | | | | | | The real hardware does not produce interrupts in LQSPI mode. Inhibit generation of interrupts when the LQ_MODE bit is set. Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@gmail.com> Message-id: dff794a06872009ea7e5733ce6adcff94d18bbd0.1369117359.git.peter.crosthwaite@xilinx.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* xilinx_spips: Make interrupts clear on readPeter Crosthwaite2013-06-031-0/+4
| | | | | | | | | | By default these interrupts are clear on read. Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@gmail.com> Message-id: 999ff0091ed3cc3969a431bf55c00ef934cecc8e.1369117359.git.peter.crosthwaite@xilinx.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* xilinx_spips: seperate SPI and QSPI as two classesPeter Crosthwaite2013-06-031-14/+55
| | | | | | | | | | | Make SPI and QSPI different classes. QSPIPS is setup as a child of SPIPS. Only QSPI has the LQSPI functionality, so move all that to the child class. Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@gmail.com> Message-id: 2cdd0cadb5ba77ca02fde5cae627852dc9a64c71.1369117359.git.peter.crosthwaite@xilinx.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* hw: move SSI controllers to hw/ssi/, configure via default-configs/Paolo Bonzini2013-04-084-0/+1357
| | | | Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
* hw: move target-independent files to subdirectoriesPaolo Bonzini2013-04-083-0/+484
| | | | | | | This patch tackles all files that are compiled once, moving them to subdirectories of hw/. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
* hw: make subdirectories for devicesPaolo Bonzini2013-04-081-0/+0
Prepare the new directory structure. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
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