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| author | Peter Crosthwaite | 2013-06-03 18:17:41 +0200 |
|---|---|---|
| committer | Peter Maydell | 2013-06-03 18:17:41 +0200 |
| commit | 87920b44a1e04a45bf74ee0a88a2dfa51c65acdb (patch) | |
| tree | 8abd0ef8458dda854108872264c3ac7382ee61c7 /hw/ssi | |
| parent | xilinx_spips: seperate SPI and QSPI as two classes (diff) | |
| download | qemu-87920b44a1e04a45bf74ee0a88a2dfa51c65acdb.tar.gz qemu-87920b44a1e04a45bf74ee0a88a2dfa51c65acdb.tar.xz qemu-87920b44a1e04a45bf74ee0a88a2dfa51c65acdb.zip | |
xilinx_spips: Make interrupts clear on read
By default these interrupts are clear on read.
Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@gmail.com>
Message-id: 999ff0091ed3cc3969a431bf55c00ef934cecc8e.1369117359.git.peter.crosthwaite@xilinx.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'hw/ssi')
| -rw-r--r-- | hw/ssi/xilinx_spips.c | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/hw/ssi/xilinx_spips.c b/hw/ssi/xilinx_spips.c index 734adf0ea7..261d948ba7 100644 --- a/hw/ssi/xilinx_spips.c +++ b/hw/ssi/xilinx_spips.c @@ -330,6 +330,10 @@ static uint64_t xilinx_spips_read(void *opaque, hwaddr addr, mask = 0x0002FFFF; break; case R_INTR_STATUS: + ret = s->regs[addr] & IXR_ALL; + s->regs[addr] = 0; + DB_PRINT("addr=" TARGET_FMT_plx " = %x\n", addr * 4, ret); + return ret; case R_INTR_MASK: mask = IXR_ALL; break; |