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* Merge tag 'pull-target-arm-20220422-1' of https://git.linaro.org/people/pmayd...Richard Henderson2022-04-2211-270/+1584
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| * hw/arm/smmuv3: Pass the actual perm to returned IOMMUTLBEntry in smmuv3_trans...Xiang Chen2022-04-221-1/+1
| * hw/arm/virt: Support TCG GICv4Peter Maydell2022-04-221-17/+53
| * hw/arm/virt: Abstract out calculation of redistributor region capacityPeter Maydell2022-04-221-7/+4Star
| * hw/arm/virt: Use VIRT_GIC_VERSION_* enum values in create_gic()Peter Maydell2022-04-221-8/+23
| * hw/intc/arm_gicv3: Allow 'revision' property to be set to 4Peter Maydell2022-04-222-5/+12
| * hw/intc/arm_gicv3: Update ID and feature registers for GICv4Peter Maydell2022-04-226-12/+32
| * hw/intc/arm_gicv3_redist: Implement gicv3_redist_inv_vlpi()Peter Maydell2022-04-221-2/+5
| * hw/intc/arm_gicv3_redist: Implement gicv3_redist_vinvall()Peter Maydell2022-04-221-1/+7
| * hw/intc/arm_gicv3_redist: Implement gicv3_redist_mov_vlpi()Peter Maydell2022-04-221-2/+18
| * hw/intc/arm_gicv3_redist: Use set_pending_table_bit() in mov handlingPeter Maydell2022-04-221-8/+1Star
| * hw/intc/arm_gicv3_redist: Implement gicv3_redist_vlpi_pending()Peter Maydell2022-04-221-2/+21
| * hw/intc/arm_gicv3_redist: Implement gicv3_redist_process_vlpi()Peter Maydell2022-04-221-4/+44
| * hw/intc/arm_gicv3_redist: Factor out "update bit in pending table" codePeter Maydell2022-04-221-19/+30
| * hw/intc/arm_gicv3_redist: Recalculate hppvlpi on VPENDBASER writesPeter Maydell2022-04-221-3/+84
| * hw/intc/arm_gicv3_redist: Factor out "update hpplpi for all LPIs" logicPeter Maydell2022-04-221-20/+46
| * hw/intc/arm_gicv3_redist: Factor out "update hpplpi for one LPI" logicPeter Maydell2022-04-221-27/+47
| * hw/intc/arm_gicv3_cpuif: Don't recalculate maintenance irq unnecessarilyPeter Maydell2022-04-221-5/+5
| * hw/intc/arm_gicv3_cpuif: Support vLPIsPeter Maydell2022-04-225-6/+137
| * hw/intc/arm_gicv3_cpuif: Split "update vIRQ/vFIQ" from gicv3_cpuif_virt_update()Peter Maydell2022-04-223-25/+53
| * hw/intc/arm_gicv3: Implement new GICv4 redistributor registersPeter Maydell2022-04-223-0/+99
| * hw/intc/arm_gicv3: Implement GICv4's new redistributor framePeter Maydell2022-04-223-5/+26
| * hw/intc/arm_gicv3_its: Implement VINVALLPeter Maydell2022-04-224-0/+45
| * hw/intc/arm_gicv3_its: Implement VMOVIPeter Maydell2022-04-224-0/+116
| * hw/intc/arm_gicv3_its: Implement INV for virtual interruptsPeter Maydell2022-04-223-2/+31
| * hw/intc/arm_gicv3_its: Implement INV command properlyPeter Maydell2022-04-224-2/+74
| * hw/intc/arm_gicv3_its: Implement VSYNCPeter Maydell2022-04-223-0/+13
| * hw/intc/arm_gicv3_its: Implement VMOVPPeter Maydell2022-04-223-0/+85
| * hw/intc/arm_gicv3: Keep pointers to every connected ITSPeter Maydell2022-04-223-0/+6
| * hw/intc/arm_gicv3_its: Handle virtual interrupts in process_its_cmd()Peter Maydell2022-04-224-2/+125
| * hw/intc/arm_gicv3_its: Split out process_its_cmd() physical interrupt codePeter Maydell2022-04-221-17/+32
| * hw/intc/arm_gicv3_its: Factor out CTE lookup sequencePeter Maydell2022-04-221-70/+39Star
| * hw/intc/arm_gicv3_its: Factor out "find ITE given devid, eventid"Peter Maydell2022-04-221-50/+54
| * hw/intc/arm_gicv3_its: Distinguish success and error cases of CMD_CONTINUEPeter Maydell2022-04-221-13/+16
| * hw/intc/arm_gicv3_its: Implement VMAPPPeter Maydell2022-04-223-0/+102
| * hw/intc/arm_gicv3_its: Implement VMAPI and VMAPTIPeter Maydell2022-04-223-0/+102
| * hw/intc/arm_gicv3_its: Implement GITS_BASER2 for GICv4Peter Maydell2022-04-222-0/+41
| * hw/intc/arm_gicv3_its: Factor out "is intid a valid LPI ID?"Peter Maydell2022-04-221-3/+7
| * hw/intc/arm_gicv3: Report correct PIDR0 values for ID registersPeter Maydell2022-04-224-5/+16
| * hw/intc/arm_gicv3: Insist that redist region capacity matches CPU countPeter Maydell2022-04-221-2/+2
| * hw/intc/arm_gicv3: Sanity-check num-cpu propertyPeter Maydell2022-04-221-0/+4
| * hw/intc/arm_gicv3_its: Add missing blank linePeter Maydell2022-04-221-0/+1
* | Merge tag 'pull-riscv-to-apply-20220422-1' of github.com:alistair23/qemu into...Richard Henderson2022-04-227-45/+791
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| * hw/riscv: boot: Support 64bit fdt address.Dylan Jhong2022-04-221-5/+7
| * hw/intc: riscv_aclint: Add reset function of ACLINT devicesJim Shu2022-04-221-0/+39
| * hw/intc: Make RISC-V ACLINT mtime MMIO register writableFrank Chang2022-04-221-21/+50
| * hw/intc: Support 32/64-bit mtimecmp and mtime accesses in RISC-V ACLINTFrank Chang2022-04-221-15/+27
| * hw/intc: Add .impl.[min|max]_access_size declaration in RISC-V ACLINTFrank Chang2022-04-221-0/+4
| * hw/riscv: virt: fix DT property mmu-type when CPU mmu option is disabledNiklas Cassel2022-04-221-2/+8
| * hw/riscv: virt: Exit if the user provided -bios in combination with KVMRalf Ramsauer2022-04-221-4/+10
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