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path: root/include/hw/riscv/microchip_pfsoc.h
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* hw/riscv: microchip_pfsoc: add QSPI NOR flashVitaly Wool2020-12-181-0/+3
* hw/riscv: microchip_pfsoc: Hook the I2C1 controllerBin Meng2020-11-031-0/+1
* hw/riscv: microchip_pfsoc: Correct DDR memory mapBin Meng2020-11-031-1/+4
* hw/riscv: microchip_pfsoc: Map the reserved memory at address 0Bin Meng2020-11-031-0/+1
* hw/riscv: microchip_pfsoc: Connect the SYSREG moduleBin Meng2020-11-031-0/+2
* hw/riscv: microchip_pfsoc: Connect the IOSCB moduleBin Meng2020-11-031-1/+3
* hw/riscv: microchip_pfsoc: Connect DDR memory controller modulesBin Meng2020-11-031-0/+5
* hw/riscv: microchip_pfsoc: Hook GPIO controllersBin Meng2020-09-101-0/+3
* hw/riscv: microchip_pfsoc: Connect 2 Cadence GEMsBin Meng2020-09-101-0/+7
* hw/riscv: microchip_pfsoc: Connect a DMA controllerBin Meng2020-09-101-0/+11
* hw/riscv: microchip_pfsoc: Connect a Cadence SDHCI controller and an SD cardBin Meng2020-09-101-0/+4
* hw/riscv: microchip_pfsoc: Connect 5 MMUARTsBin Meng2020-09-101-0/+20
* hw/riscv: Initial support for Microchip PolarFire SoC Icicle Kit boardBin Meng2020-09-101-0/+88
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