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Experimental fork of QEMU with video encoding patches
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sifive_e.h
Commit message (
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Author
Age
Files
Lines
*
sifive_e: Rename memmap enum constants
Eduardo Habkost
2020-09-18
1
-19
/
+19
*
hw/riscv: Move sifive_gpio model to hw/gpio
Bin Meng
2020-09-10
1
-1
/
+1
*
sifive_e: Support the revB machine
Alistair Francis
2020-06-19
1
-0
/
+1
*
riscv: Fix type of SiFive[EU]SocState, member parent_obj
Markus Armbruster
2020-06-15
1
-1
/
+1
*
riscv: sifive_e: Manually define the machine
Alistair Francis
2020-06-03
1
-0
/
+4
*
riscv: Add a sifive_cpu.h to include both E and U cpu type defines
Bin Meng
2019-09-17
1
-6
/
+1
*
include: Make headers more self-contained
Markus Armbruster
2019-08-16
1
-0
/
+1
*
RISC-V: Fix a memory leak when realizing a sifive_e
Palmer Dabbelt
2019-06-24
1
-0
/
+2
*
SiFive RISC-V GPIO Device
Fabien Chouteau
2019-05-24
1
-2
/
+6
*
riscv: plic: Fix incorrect irq calculation
Alistair Francis
2019-04-05
1
-1
/
+1
*
hw/riscv/sifive_e: Create a SiFive E SoC object
Alistair Francis
2018-07-06
1
-2
/
+14
*
RISC-V: Remove unused class definitions
Michael Clark
2018-05-06
1
-5
/
+0
*
SiFive Freedom E Series RISC-V Machine
Michael Clark
2018-03-06
1
-0
/
+79