summaryrefslogtreecommitdiffstats
path: root/include/hw/riscv/sifive_u.h
Commit message (Expand)AuthorAgeFilesLines
* hw/riscv: sifive_u: Use the PLIC config helper functionAlistair Francis2021-10-281-1/+0Star
* sifive_u: Connect the SiFive PWM deviceAlistair Francis2021-09-201-1/+13
* hw/riscv: sifive_u: Change SIFIVE_U_GEM_IRQ to decimal valueBin Meng2021-03-041-1/+1
* hw/riscv: sifive_u: Add QSPI2 controller and connect an SD cardBin Meng2021-03-041-0/+3
* hw/riscv: sifive_u: Add QSPI0 controller and connect a flashBin Meng2021-03-041-0/+4
* hw/riscv: sifive_u: Allow specifying the CPUAlistair Francis2020-10-221-0/+1
* sifive_u: Rename memmap enum constantsEduardo Habkost2020-09-181-17/+17
* hw/riscv: Move sifive_gpio model to hw/gpioBin Meng2020-09-101-1/+1
* hw/riscv: Move sifive_u_otp model to hw/miscBin Meng2020-09-101-1/+1
* hw/riscv: Move sifive_u_prci model to hw/miscBin Meng2020-09-101-1/+1
* hw/riscv: sifive_u: Connect a DMA controllerBin Meng2020-09-101-0/+11
* hw/riscv: sifive_u: Add a dummy L2 cache controller deviceBin Meng2020-08-221-0/+4
* hw/riscv: sifive_u: Add a dummy DDR memory controller deviceBin Meng2020-06-191-0/+1
* hw/riscv: sifive_u: Support different boot source per MSEL pin stateBin Meng2020-06-191-0/+6
* hw/riscv: sifive_u: Add a new property msel for MSEL pin stateBin Meng2020-06-191-0/+1
* hw/riscv: sifive_u: Hook a GPIO controllerBin Meng2020-06-191-0/+19
* riscv: Fix type of SiFive[EU]SocState, member parent_objMarkus Armbruster2020-06-151-1/+1
* riscv/sifive_u: Add a serial property to the sifive_u machineBin Meng2020-04-291-0/+1
* riscv/sifive_u: Add a serial property to the sifive_u SoCAlistair Francis2020-04-291-0/+2
* riscv/sifive_u: Add the start-in-flash propertyAlistair Francis2019-10-281-0/+2
* riscv/sifive_u: Manually define the machineAlistair Francis2019-10-281-1/+6
* riscv/sifive_u: Add QSPI memory regionAlistair Francis2019-10-281-0/+1
* riscv/sifive_u: Add L2-LIM cache memoryAlistair Francis2019-10-281-0/+1
* riscv: hw: Drop "clock-frequency" property of cpu nodesBin Meng2019-10-281-1/+0Star
* riscv: sifive_u: Remove handcrafted clock nodes for UART and ethernetBin Meng2019-09-171-2/+1Star
* riscv: sifive_u: Fix broken GEM supportBin Meng2019-09-171-1/+2
* riscv: sifive_u: Instantiate OTP memory with a serial numberBin Meng2019-09-171-0/+3
* riscv: sifive_u: Update UART base addresses and IRQsBin Meng2019-09-171-2/+2
* riscv: sifive_u: Add PRCI block to the SoCBin Meng2019-09-171-0/+3
* riscv: sifive_u: Generate hfclk and rtcclk nodesBin Meng2019-09-171-0/+2
* riscv: sifive_u: Update hart configuration to reflect the real FU540 SoCBin Meng2019-09-171-1/+5
* riscv: sifive_u: Set the minimum number of cpus to 2Bin Meng2019-09-171-0/+2
* riscv: Add a sifive_cpu.h to include both E and U cpu type definesBin Meng2019-09-171-6/+1Star
* include: Make headers more self-containedMarkus Armbruster2019-08-161-0/+1
* riscv: plic: Fix incorrect irq calculationAlistair Francis2019-04-051-2/+2
* sifive_u: Add clock DT node for GEM ethernetAnup Patel2018-12-201-1/+2
* hw/riscv/sifive_u: Connect the Cadence GEM Ethernet deviceAlistair Francis2018-07-061-2/+7
* hw/riscv/sifive_u: Create a SiFive U SoC objectAlistair Francis2018-07-061-2/+14
* RISC-V: Remove unused class definitionsMichael Clark2018-05-061-5/+0Star
* RISC-V: Replace hardcoded constants with enum valuesMichael Clark2018-05-061-0/+4
* SiFive Freedom U Series RISC-V MachineMichael Clark2018-03-061-0/+69
generated by cgit v1.2.3-55-g7522 (git 2.39.0) at 2024-12-12 03:00:39 +0100