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path: root/include/hw/riscv
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* hw/riscv: virt: Enable booting S-mode firmware from pflashSunil V L2022-10-141-0/+1
* hw/riscv/sifive_e: Fix inheritance of SiFiveEStateBernhard Beschow2022-09-261-1/+2
* hw/riscv: opentitan: Expose the resetvec as a SoC propertyAlistair Francis2022-09-261-0/+2
* hw/riscv: virt: fix the plic's address cellsConor Dooley2022-09-071-0/+1
* hw/riscv: microchip_pfsoc: fix kernel panics due to missing peripheralsConor Dooley2022-09-071-1/+13
* hw/riscv: opentitan: bump opentitan versionWilfred Mallawa2022-09-071-5/+6
* hw/riscv: remove 'fdt' param from riscv_setup_rom_reset_vec()Daniel Henrique Barboza2022-09-071-1/+1
* Clean up header guards that don't match their file nameMarkus Armbruster2022-05-112-4/+5
* hw/riscv: virt: Create a platform busAlistair Francis2022-04-291-1/+6
* hw/riscv: virt: Add a machine done notifierAlistair Francis2022-04-291-0/+1
* hw/riscv: boot: Support 64bit fdt address.Dylan Jhong2022-04-221-2/+2
* riscv: opentitan: Connect opentitan SPI HostWilfred Mallawa2022-04-221-9/+21
* hw: riscv: opentitan: fixup SPI addressesWilfred Mallawa2022-03-031-1/+3
* hw/riscv: virt: Increase maximum number of allowed CPUsAnup Patel2022-03-031-1/+1
* hw/riscv: virt: Add optional AIA IMSIC support to virt machineAnup Patel2022-03-031-3/+14
* hw/riscv: virt: Add optional AIA APLIC support to virt machineAnup Patel2022-03-031-6/+20
* hw/riscv: Remove macros for ELF BIOS image namesAnup Patel2022-01-211-2/+0Star
* hw/riscv: spike: Allow using binary firmware as biosAnup Patel2022-01-211-0/+1
* target/riscv: Support start kernel directly by KVMYifei Jiang2022-01-211-0/+1
* hw/riscv: virt: Allow support for 32 coresAlistair Francis2022-01-081-1/+1
* hw/riscv: microchip_pfsoc: Use the PLIC config helper functionAlistair Francis2021-10-281-1/+0Star
* hw/riscv: sifive_u: Use the PLIC config helper functionAlistair Francis2021-10-281-1/+0Star
* hw/riscv: boot: Add a PLIC config string functionAlistair Francis2021-10-281-0/+2
* hw/riscv: virt: Don't use a macro for the PLIC configurationAlistair Francis2021-10-281-1/+0Star
* hw/riscv: opentitan: Update to the latest buildAlistair Francis2021-10-221-3/+3
* hw/riscv: virt: Add optional ACLINT support to virt machineAnup Patel2021-09-201-0/+2
* sifive_u: Connect the SiFive PWM deviceAlistair Francis2021-09-201-1/+13
* hw/riscv: opentitan: Add the flash aliasAlistair Francis2021-07-151-0/+2
* hw/riscv: opentitan: Add the unimplement rv_core_ibex_periAlistair Francis2021-07-151-0/+1
* hw/riscv: OpenTitan: Connect the mtime and mtimecmp timerAlistair Francis2021-06-241-1/+4
* hw/riscv: Use macros for BIOS image namesBin Meng2021-06-081-0/+5
* hw/opentitan: Update the interrupt layoutAlistair Francis2021-05-111-8/+8
* hw/riscv: Connect Shakti UART to Shakti platformVijai Kumar K2021-05-111-0/+2
* riscv: Add initial support for Shakti C machineVijai Kumar K2021-05-111-0/+73
* hw/riscv: microchip_pfsoc: Map EMMC/SD mux registerBin Meng2021-03-231-0/+1
* hw/riscv: Add fw_cfg support to virtAsherah Connor2021-03-231-0/+2
* hw/riscv: migrate fdt field to generic MachineStateAlex Bennée2021-03-101-1/+0Star
* hw/riscv: sifive_u: Change SIFIVE_U_GEM_IRQ to decimal valueBin Meng2021-03-041-1/+1
* hw/riscv: sifive_u: Add QSPI2 controller and connect an SD cardBin Meng2021-03-041-0/+3
* hw/riscv: sifive_u: Add QSPI0 controller and connect a flashBin Meng2021-03-041-0/+4
* riscv: Pass RISCVHartArrayState by pointerAlistair Francis2021-01-161-3/+3
* riscv/opentitan: Update the OpenTitan memory layoutAlistair Francis2020-12-181-6/+17
* hw/riscv: Use the CPU to determine if 32-bitAlistair Francis2020-12-181-3/+5
* hw/riscv: boot: Remove compile time XLEN checksAlistair Francis2020-12-181-3/+5
* riscv: virt: Remove target macro conditionalsAlistair Francis2020-12-181-6/+0Star
* riscv: spike: Remove target macro conditionalsAlistair Francis2020-12-181-6/+0Star
* hw/riscv: microchip_pfsoc: add QSPI NOR flashVitaly Wool2020-12-181-0/+3
* hw/riscv: microchip_pfsoc: Hook the I2C1 controllerBin Meng2020-11-031-0/+1
* hw/riscv: microchip_pfsoc: Correct DDR memory mapBin Meng2020-11-031-1/+4
* hw/riscv: microchip_pfsoc: Map the reserved memory at address 0Bin Meng2020-11-031-0/+1
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