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| * | spapr: Simplify handling of pre ISA 3.0 guest workaround handlingDavid Gibson2019-10-041-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Certain old guest versions don't understand the radix MMU introduced with POWER ISA 3.0, but incorrectly select it if presented with the option at CAS time. We workaround this in qemu by explicitly excluding the radix (and other ISA 3.0 linked) options if the guest doesn't explicitly note support for ISA 3.0. This is handled by the 'cas_legacy_guest_workaround' flag, which is pretty vague. Rename it to 'cas_pre_isa3_guest' to be clearer about what it's for. In addition, we unnecessarily call spapr_populate_pa_features() with different options when initially constructing the device tree and when adjusting it at CAS time. At the initial construct time cas_pre_isa3_guest is already false, so we can still use the flag, rather than explicitly overriding it to be false at the callsite. Signed-off-by: David Gibson <david@gibson.dropbear.id.au> Reviewed-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Greg Kurz <groug@kaod.org> Reviewed-by: Alexey Kardashevskiy <aik@ozlabs.ru>
| * | spapr/irq: Introduce an ics_irq_free() helperCédric Le Goater2019-10-041-0/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | It will help us to discard interrupt numbers which have not been claimed in the next patch. Signed-off-by: Cédric Le Goater <clg@kaod.org> Message-Id: <20190911133937.2716-2-clg@kaod.org> Reviewed-by: Greg Kurz <groug@kaod.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
| * | hw/ppc/pnv_homer: add PowerNV homer device modelBalamuruhan S2019-10-042-0/+56
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | add PnvHomer device model to emulate homer memory access for pstate table, occ-sensors, slw, occ static and dynamic values for Power8 and Power9 chips. Signed-off-by: Balamuruhan S <bala24@linux.ibm.com> Message-Id: <20190912093056.4516-4-bala24@linux.ibm.com> Reviewed-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
| * | hw/ppc/pnv_occ: add sram device model for occ common areaBalamuruhan S2019-10-041-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | emulate occ common area region with occ sram device model which occ and skiboot uses it to communicate regarding sensors, slw and HWMON in PowerNV emulated host. Reviewed-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: Balamuruhan S <bala24@linux.ibm.com> Message-Id: <20190912093056.4516-3-bala24@linux.ibm.com> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
| * | hw/ppc/pnv_xscom: retrieve homer/occ base address from PBA BARsBalamuruhan S2019-10-041-0/+18
| |/ | | | | | | | | | | | | | | | | | | | | | | During PowerNV boot skiboot populates the device tree by retrieving base address of homer/occ common area from PBA BARs and prd ipoll mask by accessing xscom read/write accesses. Reviewed-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: Balamuruhan S <bala24@linux.ibm.com> Message-Id: <20190912093056.4516-2-bala24@linux.ibm.com> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
* / vfio: Turn the container error into an Error handleEric Auger2019-10-041-1/+1
|/ | | | | | | | | | | | | The container error integer field is currently used to store the first error potentially encountered during any vfio_listener_region_add() call. However this fails to propagate detailed error messages up to the vfio_connect_container caller. Instead of using an integer, let's use an Error handle. Messages are slightly reworded to accomodate the propagation. Signed-off-by: Eric Auger <eric.auger@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
* cputlb: Remove cpu->mem_io_vaddrRichard Henderson2019-09-251-2/+0Star
| | | | | | | | | With the merge of notdirty handling into store_helper, the last user of cpu->mem_io_vaddr was removed. Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: David Hildenbrand <david@redhat.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* xen: perform XenDevice clean-up in XenBus watch handlerPaul Durrant2019-09-241-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Cleaning up offline XenDevice objects directly in xen_device_backend_changed() is dangerous as xen_device_unrealize() will modify the watch list that is being walked. Even the QLIST_FOREACH_SAFE() used in notifier_list_notify() is insufficient as *two* notifiers (for the frontend and backend watches) are removed, thus potentially rendering the 'next' pointer unsafe. The solution is to use the XenBus backend_watch handler to do the clean-up instead, as it is invoked whilst walking a separate watch list. This patch therefore adds a new 'inactive_devices' list to XenBus, to which offline devices are added by xen_device_backend_changed(). The XenBus backend_watch registration is also changed to not only invoke xen_bus_enumerate() but also a new xen_bus_cleanup() function, which will walk 'inactive_devices' and perform the necessary actions. For safety an extra 'online' check is also added to xen_bus_type_enumerate() to make sure that no attempt is made to create a new XenDevice object for a backend that is offline. NOTE: This patch also includes some cosmetic changes: - substitute the local variable name 'backend_state' in xen_bus_type_enumerate() with 'state', since there is no ambiguity with any other state in that context. - change xen_device_state_is_active() to xen_device_frontend_is_active() (and pass a XenDevice directly) since the state tests contained therein only apply to a frontend. - use 'state' rather then 'xendev->backend_state' in xen_device_backend_changed() to shorten the code. Signed-off-by: Paul Durrant <paul.durrant@citrix.com> Reviewed-by: Anthony PERARD <anthony.perard@citrix.com> Message-Id: <20190913082159.31338-4-paul.durrant@citrix.com> Signed-off-by: Anthony PERARD <anthony.perard@citrix.com>
* xen: introduce separate XenWatchList for XenDevice objectsPaul Durrant2019-09-241-0/+2
| | | | | | | | | | | | This patch uses the XenWatchList abstraction to add a separate watch list for each device. This is more scalable than walking a single notifier list for all watches and is also necessary to implement a bug-fix in a subsequent patch. Signed-off-by: Paul Durrant <paul.durrant@citrix.com> Reviewed-by: Anthony Perard <anthony.perard@citrix.com> Message-Id: <20190913082159.31338-3-paul.durrant@citrix.com> Signed-off-by: Anthony PERARD <anthony.perard@citrix.com>
* xen / notify: introduce a new XenWatchList abstractionPaul Durrant2019-09-241-1/+2
| | | | | | | | | | | | | | | | | | | | Xenstore watch call-backs are already abstracted away from XenBus using the XenWatch data structure but the associated NotifierList manipulation and file handle registration is still open coded in various xen_bus_...() functions. This patch creates a new XenWatchList data structure to allow these interactions to be abstracted away from XenBus as well. This is in preparation for a subsequent patch which will introduce separate watch lists for XenBus and XenDevice objects. NOTE: This patch also introduces a new notifier_list_empty() helper function for the purposes of adding an assertion that a XenWatchList is not freed whilst its associated NotifierList is still occupied. Signed-off-by: Paul Durrant <paul.durrant@citrix.com> Reviewed-by: Anthony Perard <anthony.perard@citrix.com> Message-Id: <20190913082159.31338-2-paul.durrant@citrix.com> Signed-off-by: Anthony PERARD <anthony.perard@citrix.com>
* pc: Add an SMB0 ACPI device to q35Corey Minyard2019-09-201-0/+2
| | | | | | | | | | | | | | | | This is so I2C devices can be found in the ACPI namespace. Currently that's only IPMI, but devices can be easily added now. Adding the devices required some PCI information, and the bus itself to be added to the PCMachineState structure. Note that this only works on Q35, the ACPI for PIIX4 is not capable of handling an SMBus device. Cc: Michael S. Tsirkin <mst@redhat.com> Cc: Igor Mammedov <imammedo@redhat.com> Signed-off-by: Corey Minyard <cminyard@mvista.com> Reviewed-by: Paolo Bonzini <pbonzini@redhat.com>
* ipmi: Fix SSIF ACPI handling to use the right CRSCorey Minyard2019-09-201-1/+1
| | | | | | | | Pass in the CRS so that it can be set to the SMBus for IPMI later. Cc: Michael S. Tsirkin <mst@redhat.com> Cc: Igor Mammedov <imammedo@redhat.com> Signed-off-by: Corey Minyard <cminyard@mvista.com>
* acpi: Add i2c serial bus CRS handlingCorey Minyard2019-09-201-0/+18
| | | | | | | | | This will be required for getting IPMI SSIF (SMBus interface) into the ACPI tables. Cc: Michael S. Tsirkin <mst@redhat.com> Cc: Igor Mammedov <imammedo@redhat.com> Signed-off-by: Corey Minyard <cminyard@mvista.com>
* ipmi: Add PCI IPMI interfacesCorey Minyard2019-09-201-0/+1
| | | | | | | | | Pretty straightforward, just hook the current KCS and BT code into the PCI system with the proper configuration. Cc: Michael S. Tsirkin <mst@redhat.com> Cc: M: Marcel Apfelbaum <marcel.apfelbaum@gmail.com> Signed-off-by: Corey Minyard <cminyard@mvista.com>
* ipmi: Allow a size value to be passed for I/O spaceCorey Minyard2019-09-203-1/+8
| | | | | | | | PCI device I/O must be >= 8 bytes in length or they don't work. Allow the size to be passed in, the default size of 2 or 3 won't work. Signed-off-by: Corey Minyard <cminyard@mvista.com>
* ipmi: Split out BT-specific code from ISA BT codeCorey Minyard2019-09-201-0/+72
| | | | | | | | | | Get ready for PCI and other BT interfaces. No functional changes, just split the code into generic BT code and ISA-specific BT code. Signed-off-by: Corey Minyard <cminyard@mvista.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
* ipmi: Split out KCS-specific code from ISA KCS codeCorey Minyard2019-09-201-0/+75
| | | | | | | | | | Get ready for PCI and other KCS interfaces. No functional changes, just split the code into the generic KCS code and the ISA-specific code. Signed-off-by: Corey Minyard <cminyard@mvista.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
* qdev: Add a no default uuid propertyCorey Minyard2019-09-201-0/+7
| | | | | | | | | | | This is for IPMI, which will behave differently if the UUID is not set. Signed-off-by: Corey Minyard <cminyard@mvista.com> Cc: Fam Zheng <famz@redhat.com> Cc: Michael S. Tsirkin <mst@redhat.com> Cc: Marc-André Lureau <marcandre.lureau@redhat.com> Reviewed-by: Paolo Bonzini <pbonzini@redhat.com>
* Merge remote-tracking branch ↵Peter Maydell2019-09-1911-92/+298
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | 'remotes/palmer/tags/riscv-for-master-4.2-sf1-v3' into staging RISC-V Patches for the 4.2 Soft Freeze, Part 1, v3 This contains quite a few patches that I'd like to target for 4.2. They're mostly emulation fixes for the sifive_u board, which now much more closely matches the hardware and can therefor run the same fireware as what gets loaded onto the board. Additional user-visible improvements include: * support for loading initrd files from the command line into Linux, via /chosen/linux,initrd-{start,end} device tree nodes. * The conversion of LOG_TRACE to trace events. * The addition of clock DT nodes for our uart and ethernet. This also includes some preliminary work for the H extension patches, but does not include the H extension patches as I haven't had time to review them yet. This passes my OE boot test on 32-bit and 64-bit virt machines, as well as a 64-bit upstream Linux boot on the sifive_u machine. It has been fixed to actually pass "make check" this time. Changes since v2 (never made it to the list): * Sets the sifive_u machine default core count to 2 instead of 5. Changes since v1 <20190910190513.21160-1-palmer@sifive.com>: * Sets the sifive_u machine default core count to 5 instead of 1, as it's impossible to have a single core sifive_u machine. # gpg: Signature made Tue 17 Sep 2019 16:43:30 BST # gpg: using RSA key 00CE76D1834960DFCE886DF8EF4CA1502CCBAB41 # gpg: issuer "palmer@dabbelt.com" # gpg: Good signature from "Palmer Dabbelt <palmer@dabbelt.com>" [unknown] # gpg: aka "Palmer Dabbelt <palmer@sifive.com>" [unknown] # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: 00CE 76D1 8349 60DF CE88 6DF8 EF4C A150 2CCB AB41 * remotes/palmer/tags/riscv-for-master-4.2-sf1-v3: (48 commits) gdbstub: riscv: fix the fflags registers target/riscv: Use TB_FLAGS_MSTATUS_FS for floating point target/riscv: Fix mstatus dirty mask target/riscv: Use both register name and ABI name riscv: sifive_u: Update model and compatible strings in device tree riscv: sifive_u: Remove handcrafted clock nodes for UART and ethernet riscv: sifive_u: Fix broken GEM support riscv: sifive_u: Instantiate OTP memory with a serial number riscv: sifive: Implement a model for SiFive FU540 OTP riscv: roms: Update default bios for sifive_u machine riscv: sifive_u: Change UART node name in device tree riscv: sifive_u: Update UART base addresses and IRQs riscv: sifive_u: Reference PRCI clocks in UART and ethernet nodes riscv: sifive_u: Add PRCI block to the SoC riscv: sifive_u: Generate hfclk and rtcclk nodes riscv: sifive: Implement PRCI model for FU540 riscv: sifive_u: Update PLIC hart topology configuration string riscv: sifive_u: Update hart configuration to reflect the real FU540 SoC riscv: sifive_u: Set the minimum number of cpus to 2 riscv: hart: Add a "hartid-base" property to RISC-V hart array ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * riscv: sifive_u: Remove handcrafted clock nodes for UART and ethernetBin Meng2019-09-171-2/+1Star
| | | | | | | | | | | | | | | | | | | | | | In the past we did not have a model for PRCI, hence two handcrafted clock nodes ("/soc/ethclk" and "/soc/uartclk") were created for the purpose of supplying hard-coded clock frequencies. But now since we have added the PRCI support in QEMU, we don't need them any more. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
| * riscv: sifive_u: Fix broken GEM supportBin Meng2019-09-171-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | At present the GEM support in sifive_u machine is seriously broken. The GEM block register base was set to a weird number (0x100900FC), which for no way could work with the cadence_gem model in QEMU. Not like other GEM variants, the FU540-specific GEM has a management block to control 10/100/1000Mbps link speed changes, that is mapped to 0x100a0000. We can simply map it into MMIO space without special handling using create_unimplemented_device(). Update the GEM node compatible string to use the official name used by the upstream Linux kernel, and add the management block reg base & size to the <reg> property encoding. Tested with upstream U-Boot and Linux kernel MACB drivers. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
| * riscv: sifive_u: Instantiate OTP memory with a serial numberBin Meng2019-09-171-0/+3
| | | | | | | | | | | | | | | | | | | | This adds an OTP memory with a given serial number to the sifive_u machine. With such support, the upstream U-Boot for sifive_fu540 boots out of the box on the sifive_u machine. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
| * riscv: sifive: Implement a model for SiFive FU540 OTPBin Meng2019-09-171-0/+80
| | | | | | | | | | | | | | | | | | | | | | This implements a simple model for SiFive FU540 OTP (One-Time Programmable) Memory interface, primarily for reading out the stored serial number from the first 1 KiB of the 16 KiB OTP memory reserved by SiFive for internal use. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
| * riscv: sifive_u: Update UART base addresses and IRQsBin Meng2019-09-171-2/+2
| | | | | | | | | | | | | | | | | | | | This updates the UART base address and IRQs to match the hardware. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Jonathan Behrens <fintelia@gmail.com> Acked-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Chih-Min Chao <chihmin.chao@sifive.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
| * riscv: sifive_u: Reference PRCI clocks in UART and ethernet nodesBin Meng2019-09-171-0/+10
| | | | | | | | | | | | | | | | | | | | Now that we have added a PRCI node, update existing UART and ethernet nodes to reference PRCI as their clock sources, to keep in sync with the Linux kernel device tree. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
| * riscv: sifive_u: Add PRCI block to the SoCBin Meng2019-09-171-0/+3
| | | | | | | | | | | | | | | | | | Add PRCI mmio base address and size mappings to sifive_u machine, and generate the corresponding device tree node. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
| * riscv: sifive_u: Generate hfclk and rtcclk nodesBin Meng2019-09-171-0/+2
| | | | | | | | | | | | | | | | | | To keep in sync with Linux kernel device tree, generate hfclk and rtcclk nodes in the device tree, to be referenced by PRCI node. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
| * riscv: sifive: Implement PRCI model for FU540Bin Meng2019-09-171-0/+81
| | | | | | | | | | | | | | | | | | This adds a simple PRCI model for FU540 (sifive_u). It has different register layout from the existing PRCI model for FE310 (sifive_e). Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
| * riscv: sifive_u: Update hart configuration to reflect the real FU540 SoCBin Meng2019-09-171-1/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | The FU540-C000 includes a 64-bit E51 RISC-V core and four 64-bit U54 RISC-V cores. Currently the sifive_u machine only populates 4 U54 cores. Update the max cpu number to 5 to reflect the real hardware, by creating 2 CPU clusters as containers for RISC-V hart arrays to populate heterogeneous harts. The cpu nodes in the generated DTS have been updated as well. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
| * riscv: sifive_u: Set the minimum number of cpus to 2Bin Meng2019-09-171-0/+2
| | | | | | | | | | | | | | | | | | | | It is not useful if we only have one management CPU. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> [Palmer: Set default CPUs to 2] Reviewed-by: Palmer Dabbelt <palmer@sifive.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
| * riscv: hart: Add a "hartid-base" property to RISC-V hart arrayBin Meng2019-09-171-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | At present each hart's hartid in a RISC-V hart array is assigned the same value of its index in the hart array. But for a system that has multiple hart arrays, this is not the case any more. Add a new "hartid-base" property so that hartid number can be assigned based on the property value. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
| * riscv: Add a sifive_cpu.h to include both E and U cpu type definesBin Meng2019-09-173-12/+33
| | | | | | | | | | | | | | | | | | Group SiFive E and U cpu type defines into one header file. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
| * riscv: sifive_e: prci: Update the PRCI register block sizeBin Meng2019-09-171-0/+2
| | | | | | | | | | | | | | | | | | | | Currently the PRCI register block size is set to 0x8000, but in fact 0x1000 is enough, which is also what the manual says. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Chih-Min Chao <chihmin.chao@sifive.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
| * riscv: sifive: Rename sifive_prci.{c, h} to sifive_e_prci.{c, h}Bin Meng2019-09-172-71/+69Star
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Current SiFive PRCI model only works with sifive_e machine, as it only emulates registers or PRCI block in the FE310 SoC. Rename the file name to make it clear that it is for sifive_e. This also prefix "sifive_e"/"SIFIVE_E" for all macros, variables and functions. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Chih-Min Chao <chihmin.chao@sifive.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
| * riscv: sifive_test: Add reset functionalityBin Meng2019-09-171-1/+2
| | | | | | | | | | | | | | | | | | This adds a reset opcode for sifive_test device to trigger a system reset for testing purpose. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Palmer Dabbelt <palmer@sifive.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
| * riscv: Add a helper routine for finding firmwareBin Meng2019-09-171-0/+1
| | | | | | | | | | | | | | | | | | This adds a helper routine for finding firmware. It is currently used only for "-bios default" case. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
| * riscv: plic: Remove unused interrupt functionsAlistair Francis2019-09-171-3/+0Star
| | | | | | | | | | | | | | | | Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Jonathan Behrens <fintelia@gmail.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Reviewed-by: Chih-Min Chao <chihmin.chao@sifive.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
* | Merge remote-tracking branch 'remotes/mst/tags/for_upstream' into stagingPeter Maydell2019-09-172-0/+10
|\ \ | |/ |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | virtio,vhost,pc: features, fixes, cleanups. Virtio 1.0 support for virtio-mmio. Misc fixes, cleanups. Signed-off-by: Michael S. Tsirkin <mst@redhat.com> # gpg: Signature made Mon 16 Sep 2019 16:17:30 BST # gpg: using RSA key 281F0DB8D28D5469 # gpg: Good signature from "Michael S. Tsirkin <mst@kernel.org>" [full] # gpg: aka "Michael S. Tsirkin <mst@redhat.com>" [full] # Primary key fingerprint: 0270 606B 6F3C DF3D 0B17 0970 C350 3912 AFBE 8E67 # Subkey fingerprint: 5D09 FD08 71C8 F85B 94CA 8A0D 281F 0DB8 D28D 5469 * remotes/mst/tags/for_upstream: virtio-mmio: implement modern (v2) personality (virtio-1) virtio pmem: user document intel_iommu: Remove the caching-mode check during flag change pc/q35: Disallow vfio-pci hotplug without VT-d caching mode qdev/machine: Introduce hotplug_allowed hook intel_iommu: Sanity check vfio-pci config on machine init done backends/vhost-user.c: prevent using uninitialized vqs vhost-user-blk: prevent using uninitialized vqs docs/nvdimm: add example on persistent backend setup MAINTAINERS: update virtio-rng and virtio-serial maintainer Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * qdev/machine: Introduce hotplug_allowed hookPeter Xu2019-09-162-0/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Introduce this new per-machine hook to give any machine class a chance to do a sanity check on the to-be-hotplugged device as a sanity test. This will be used for x86 to try to detect some illegal configuration of devices, e.g., possible conflictions between vfio-pci and x86 vIOMMU. Reviewed-by: Eric Auger <eric.auger@redhat.com> Signed-off-by: Peter Xu <peterx@redhat.com> Message-Id: <20190916080718.3299-3-peterx@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
* | Merge remote-tracking branch 'remotes/bonzini/tags/for-upstream' into stagingPeter Maydell2019-09-173-11/+6Star
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * Fix Patchew CI failures (myself) * i386 fw_cfg refactoring (Philippe) * pmem bugfix (Stefan) * Support for accessing cstate MSRs (Wanpeng) * exec.c cleanups (Wei Yang) * Improved throttling (Yury) * elf-ops.h coverity fix (Stefano) # gpg: Signature made Mon 16 Sep 2019 16:13:12 BST # gpg: using RSA key BFFBD25F78C7AE83 # gpg: Good signature from "Paolo Bonzini <bonzini@gnu.org>" [full] # gpg: aka "Paolo Bonzini <pbonzini@redhat.com>" [full] # Primary key fingerprint: 46F5 9FBD 57D6 12E7 BFD4 E2F7 7E15 100C CD36 69B1 # Subkey fingerprint: F133 3857 4B66 2389 866C 7682 BFFB D25F 78C7 AE83 * remotes/bonzini/tags/for-upstream: (29 commits) hw/i386/pc: Extract the x86 generic fw_cfg code hw/i386/pc: Rename pc_build_feature_control() as generic fw_cfg_build_* hw/i386/pc: Let pc_build_feature_control() take a MachineState argument hw/i386/pc: Let pc_build_feature_control() take a FWCfgState argument hw/i386/pc: Rename pc_build_smbios() as generic fw_cfg_build_smbios() hw/i386/pc: Let pc_build_smbios() take a generic MachineState argument hw/i386/pc: Let pc_build_smbios() take a FWCfgState argument hw/i386/pc: Replace PCMachineState argument with MachineState in fw_cfg_arch_create hw/i386/pc: Pass the CPUArchIdList array by argument hw/i386/pc: Pass the apic_id_limit value by argument hw/i386/pc: Pass the boot_cpus value by argument hw/i386/pc: Rename bochs_bios_init as more generic fw_cfg_arch_create hw/i386/pc: Use address_space_memory in place hw/i386/pc: Extract e820 memory layout code hw/i386/pc: Use e820_get_num_entries() to access e820_entries cpus: Fix throttling during vm_stop qemu-thread: Add qemu_cond_timedwait memory: inline and optimize devend_memop memory: fetch pmem size in get_file_size() elf-ops.h: fix int overflow in load_elf() ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * | hw/i386/pc: Extract e820 memory layout codePhilippe Mathieu-Daudé2019-09-161-11/+0Star
| | | | | | | | | | | | | | | | | | | | | | | | Suggested-by: Samuel Ortiz <sameo@linux.intel.com> Reviewed-by: Li Qiang <liq3ea@gmail.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com> Message-Id: <20190818225414.22590-3-philmd@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
| * | elf-ops.h: fix int overflow in load_elf()Stefano Garzarella2019-09-162-0/+6
| |/ | | | | | | | | | | | | | | | | | | | | This patch fixes a possible integer overflow when we calculate the total size of ELF segments loaded. Reported-by: Coverity (CID 1405299) Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Stefano Garzarella <sgarzare@redhat.com> Message-Id: <20190910124828.39794-1-sgarzare@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
* | aspeed/scu: Introduce a aspeed_scu_get_apb_freq() routineCédric Le Goater2019-09-131-5/+3Star
| | | | | | | | | | | | | | | | | | | | | | The APB frequency can be calculated directly when needed from the HPLL_PARAM and CLK_SEL register values. This removes useless state in the model. Signed-off-by: Cédric Le Goater <clg@kaod.org> Message-id: 20190904070506.1052-11-clg@kaod.org Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* | aspeed/scu: Introduce per-SoC SCU typesCédric Le Goater2019-09-131-0/+15
| | | | | | | | | | | | | | | | | | and use a class AspeedSCUClass to define each SoC characteristics. Signed-off-by: Cédric Le Goater <clg@kaod.org> Message-id: 20190904070506.1052-10-clg@kaod.org Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* | aspeed/smc: Inject errors in DMA checksumCédric Le Goater2019-09-131-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Emulate read errors in the DMA Checksum Register for high frequencies and optimistic settings of the Read Timing Compensation Register. This will help in tuning the SPI timing calibration algorithm. Errors are only injected when the property "inject_failure" is set to true as suggested by Philippe. The values below are those to expect from the first flash device of the FMC controller of a palmetto-bmc machine. Cc: Philippe Mathieu-Daudé <philmd@redhat.com> Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Joel Stanley <joel@jms.id.au> Message-id: 20190904070506.1052-8-clg@kaod.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* | aspeed/smc: Add support for DMAsCédric Le Goater2019-09-131-0/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The FMC controller on the Aspeed SoCs support DMA to access the flash modules. It can operate in a normal mode, to copy to or from the flash module mapping window, or in a checksum calculation mode, to evaluate the best clock settings for reads. The model introduces two custom address spaces for DMAs: one for the AHB window of the FMC flash devices and one for the DRAM. The latter is populated using a "dram" link set from the machine with the RAM container region. Signed-off-by: Cédric Le Goater <clg@kaod.org> Acked-by: Joel Stanley <joel@jms.id.au> Message-id: 20190904070506.1052-6-clg@kaod.org Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* | aspeed: Use consistent typenamesCédric Le Goater2019-09-131-3/+0Star
| | | | | | | | | | | | | | | | | | | | | | Improve the naming of the different controller models to ease their generation when initializing the SoC. The rename of the SMC types is breaking migration compatibility. Signed-off-by: Cédric Le Goater <clg@kaod.org> Message-id: 20190904070506.1052-5-clg@kaod.org Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* | aspeed: add a GPIO controller to the SoCRashmica Gupta2019-09-131-0/+3
| | | | | | | | | | | | | | | | Signed-off-by: Rashmica Gupta <rashmica.g@gmail.com> Reviewed-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: Cédric Le Goater <clg@kaod.org> Message-id: 20190904070506.1052-3-clg@kaod.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* | hw/gpio: Add basic Aspeed GPIO model for AST2400 and AST2500Rashmica Gupta2019-09-131-0/+100
|/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | GPIO pins are arranged in groups of 8 pins labeled A,B,..,Y,Z,AA,AB,AC. (Note that the ast2400 controller only goes up to group AB). A set has four groups (except set AC which only has one) and is referred to by the groups it is composed of (eg ABCD,EFGH,...,YZAAAB). Each set is accessed and controlled by a bank of 14 registers. These registers operate on a per pin level where each bit in the register corresponds to a pin, except for the command source registers. The command source registers operate on a per group level where bits 24, 16, 8 and 0 correspond to each group in the set. eg. registers for set ABCD: |D7...D0|C7...C0|B7...B0|A7...A0| <- GPIOs |31...24|23...16|15....8|7.....0| <- bit position Note that there are a couple of groups that only have 4 pins. There are two ways that this model deviates from the behaviour of the actual controller: (1) The only control source driving the GPIO pins in the model is the ARM model (as there currently aren't models for the LPC or Coprocessor). (2) None of the registers in the model are reset tolerant (needs integration with the watchdog). Signed-off-by: Rashmica Gupta <rashmica.g@gmail.com> Tested-by: Andrew Jeffery <andrew@aj.id.au> Reviewed-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: Cédric Le Goater <clg@kaod.org> Message-id: 20190904070506.1052-2-clg@kaod.org [clg: fixed missing header files made use of HWADDR_PRIx to fix compilation on windows ] Signed-off-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* escc: introduce a selector for the register bitLaurent Vivier2019-09-071-0/+1
| | | | | | | | | | | | | | | | | | | | | | On Sparc and PowerMac, the bit 0 of the address selects the register type (control or data) and bit 1 selects the channel (B or A). On m68k Macintosh and NeXTcube, the bit 0 selects the channel and bit 1 the register type. This patch introduces a new parameter (bit_swap) to the device interface to indicate bits usage must be swapped between registers and channels. For the moment all the machines use the bit 0, but this change will be needed to emulate the Quadra 800 or NeXTcube machine. Signed-off-by: Laurent Vivier <laurent@vivier.eu> Reviewed-by: Hervé Poussineau <hpoussin@reactos.org> [thh: added NeXTcube to the patch description] Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Tested-by: Philippe Mathieu-Daudé <philmd@redhat.com> Message-Id: <20190831074519.32613-5-huth@tuxfamily.org> Signed-off-by: Thomas Huth <huth@tuxfamily.org>
generated by cgit v1.2.3-55-g7522 (git 2.39.0) at 2025-02-04 10:52:26 +0100