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* tcg: Move helper_*_mmu decls to tcg/tcg-ldst.hRichard Henderson2021-10-132-71/+74
* accel/tcg: Move cpu_atomic decls to exec/cpu_ldst.hRichard Henderson2021-10-131-87/+0Star
* accel/tcg: re-factor plugin_inject_cb so we can assert insn_idx is validAlex Bennée2021-10-121-6/+0Star
* tcg: Split out MemOpIdx to exec/memopidx.hRichard Henderson2021-10-061-38/+1Star
* tcg: Rename TCGMemOpIdx to MemOpIdxRichard Henderson2021-10-061-37/+37
* tcg: add dup_const_tl wrapperPhilipp Tomsich2021-10-061-0/+12
* tcg: Remove tcg_global_reg_new definesBin Meng2021-09-141-2/+0Star
* tcg: Rename helper_atomic_*_mmu and provide for user-onlyRichard Henderson2021-07-211-44/+36Star
* tcg: Remove TCG_TARGET_HAS_goto_ptrRichard Henderson2021-07-101-2/+1Star
* tcg: Move tb_phys_invalidate_count to tb_ctxRichard Henderson2021-07-091-3/+0Star
* tcg: Bake tb_destroy() into tcg_region_treeLiren Wei2021-07-091-1/+0Star
* tcg: Add flags argument to tcg_gen_bswap16_*, tcg_gen_bswap32_i64Richard Henderson2021-06-291-4/+4
* tcg: Add flags argument to bswap opcodesRichard Henderson2021-06-292-5/+17
* tcg: Implement tcg_gen_vec_add{sub}32_tlLIU Zhiwei2021-06-291-0/+4
* tcg: Add tcg_gen_vec_shl{shr}{sar}8i_i32LIU Zhiwei2021-06-291-0/+10
* tcg: Add tcg_gen_vec_shl{shr}{sar}16i_i32LIU Zhiwei2021-06-291-0/+10
* tcg: Add tcg_gen_vec_add{sub}8_i32LIU Zhiwei2021-06-291-0/+6
* tcg: Add tcg_gen_vec_add{sub}16_i32LIU Zhiwei2021-06-291-0/+13
* Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20210624'...Peter Maydell2021-06-242-1/+8
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| * tcg: Make gen_dup_i32/i64() public as tcg_gen_dup_i32/i64Peter Maydell2021-06-212-1/+8
* | tcg: expose TCGCond manipulation routinesAlessandro Di Federico2021-06-192-69/+102
* | tcg/tci: Change encoding to uint32_t unitsRichard Henderson2021-06-191-2/+2
* | tcg/tci: Use ffi for callsRichard Henderson2021-06-191-0/+1
|/
* tcg: Fix documentation for tcg_constant_* vs tcg_temp_free_*Richard Henderson2021-06-141-1/+2
* tcg: Introduce tcg_remove_ops_afterRichard Henderson2021-06-141-0/+10
* tcg: Move tcg_init_ctx and tcg_ctx from accel/tcg/Richard Henderson2021-06-141-1/+0Star
* tcg: Move in_code_gen_buffer and tests to region.cRichard Henderson2021-06-111-10/+1Star
* accel/tcg: Pass down max_cpus to tcg_initRichard Henderson2021-06-111-1/+1
* tcg: Create tcg_initRichard Henderson2021-06-111-2/+1Star
* accel/tcg: Move alloc_code_gen_buffer to tcg/region.cRichard Henderson2021-06-111-1/+1
* accel/tcg: Reduce 'exec/tb-context.h' inclusionPhilippe Mathieu-Daudé2021-05-271-1/+0Star
* tcg: Add tcg_constant_tlMatheus Ferst2021-05-141-0/+2
* tcg/tci: Implement the disassembler properlyRichard Henderson2021-03-171-2/+0Star
* tcg: Restart code generation when we run out of tempsRichard Henderson2021-01-241-0/+3
* tcg: Optimize inline dup_const for MO_64Richard Henderson2021-01-221-1/+2
* tcg: Remove tcg_gen_dup{8,16,32,64}i_vecRichard Henderson2021-01-131-4/+0Star
* tcg: Remove movi and dupi opcodesRichard Henderson2021-01-131-3/+0Star
* tcg/tci: Add special tci_movi_{i32,i64} opcodesRichard Henderson2021-01-131-0/+8
* tcg: Use tcg_constant_{i32,i64,vec} with gvec expandersRichard Henderson2021-01-131-0/+1
* tcg: Use tcg_constant_{i32,i64} with tcg int expandersRichard Henderson2021-01-131-11/+2Star
* tcg: Introduce TYPE_CONST temporariesRichard Henderson2021-01-131-1/+23
* tcg: Expand TCGTemp.val to 64-bitsRichard Henderson2021-01-131-1/+1
* tcg: Add temp_readonlyRichard Henderson2021-01-131-0/+5
* tcg: Consolidate 3 bits into enum TCGTempKindRichard Henderson2021-01-131-8/+12
* tcg: Constify tcg_code_gen_epilogueRichard Henderson2021-01-071-1/+1
* tcg: Introduce tcg_tbrel_diffRichard Henderson2021-01-071-0/+13
* tcg: Make DisasContextBase.tb constRichard Henderson2021-01-071-1/+1
* tcg: Adjust tcg_register_jit for constRichard Henderson2021-01-071-1/+1
* tcg: Adjust TCGLabel for constRichard Henderson2021-01-071-1/+1
* tcg: Introduce tcg_splitwx_to_{rx,rw}Richard Henderson2021-01-071-5/+21
generated by cgit v1.2.3-55-g7522 (git 2.39.0) at 2024-12-05 04:04:04 +0100