| Commit message (Collapse) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | configure: Merge riscv32 and riscv64 host architectures | Richard Henderson | 2021-10-30 | 1 | -11/+0![]() |
| | | | | | | | | | | | | The existing code for safe-syscall.inc.S will compile without change for riscv32 and riscv64. We may also drop the meson.build stanza that merges them for tcg/. Reviewed-by: Warner Losh <imp@bsdimp.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||||
| * | linux-user: Add host dependency for RISC-V 32-bit | Alistair Francis | 2018-12-25 | 1 | -0/+11 |
| Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Michael Clark <mjc@sifive.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <76f8f9383a766dbcade883e897dec8cfef669799.1545246859.git.alistair.francis@wdc.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | |||||

