| Commit message (Expand) | Author | Age | Files | Lines |
* | cpu: move exec-all.h inclusion out of cpu.h | Paolo Bonzini | 2016-05-19 | 1 | -0/+1 |
* | include/qemu/osdep.h: Don't include qapi/error.h | Markus Armbruster | 2016-03-22 | 1 | -0/+1 |
* | target-arm: cpu: Move cpu_is_big_endian to header | Peter Crosthwaite | 2016-03-04 | 1 | -16/+3 |
* | target-arm: implement SCTLR.B, drop bswap_code | Paolo Bonzini | 2016-03-04 | 1 | -1/+1 |
* | target-arm: Add the pmceid0 and pmceid1 registers | Alistair Francis | 2016-02-18 | 1 | -0/+2 |
* | target-arm: Implement checking of fired watchpoint | Sergey Fedorov | 2016-02-11 | 1 | -0/+1 |
* | target-arm: Don't report presence of EL2 if it doesn't exist | Peter Maydell | 2016-02-03 | 1 | -0/+9 |
* | gdb: provide the name of the architecture in the target.xml | David Hildenbrand | 2016-01-27 | 1 | -0/+12 |
* | target-arm: Implement cpu_get_phys_page_attrs_debug | Peter Maydell | 2016-01-21 | 1 | -1/+1 |
* | target-arm: Implement asidx_from_attrs | Peter Maydell | 2016-01-21 | 1 | -0/+1 |
* | target-arm: Add QOM property for Secure memory region | Peter Maydell | 2016-01-21 | 1 | -0/+32 |
* | target-arm: Clean up includes | Peter Maydell | 2016-01-18 | 1 | -0/+1 |
* | target-arm: support QMP dump-guest-memory | Andrew Jones | 2016-01-15 | 1 | -0/+2 |
* | error: Strip trailing '\n' from error string arguments (again) | Markus Armbruster | 2016-01-13 | 1 | -1/+1 |
* | target-arm: raise exception on misaligned LDREX operands | Andrew Baumann | 2015-12-17 | 1 | -0/+1 |
* | qdev: Protect device-list-properties against broken devices | Markus Armbruster | 2015-10-09 | 1 | -0/+11 |
* | target-arm: Refactor CPU affinity handling | Pavel Fedin | 2015-09-07 | 1 | -1/+1 |
* | arm: Remove hw_error() usages. | Peter Crosthwaite | 2015-09-07 | 1 | -2/+2 |
* | arm: cpu: assert() on no-EL2 virt IRQ error condition. | Peter Crosthwaite | 2015-09-07 | 1 | -4/+1 |
* | target-arm: Add the AArch64 view of the Secure physical timer | Peter Maydell | 2015-08-13 | 1 | -0/+2 |
* | target-arm: Add debug check for mismatched cpreg resets | Peter Maydell | 2015-08-13 | 1 | -0/+23 |
* | target-arm: Add the Hypervisor timer | Edgar E. Iglesias | 2015-08-13 | 1 | -0/+2 |
* | disas: arm: QOMify target specific disas setup | Peter Crosthwaite | 2015-07-09 | 1 | -0/+35 |
* | cpu: Change cpu_exec_init() arg to cpu, not env | Peter Crosthwaite | 2015-07-09 | 1 | -1/+1 |
* | cpu: Add Error argument to cpu_exec_init() | Bharata B Rao | 2015-07-09 | 1 | -1/+1 |
* | Include qapi/qmp/qerror.h exactly where needed | Markus Armbruster | 2015-06-22 | 1 | -1/+0 |
* | target-arm: Add support for Cortex-R5 | Peter Crosthwaite | 2015-06-19 | 1 | -0/+38 |
* | target-arm: Add registers for PMSAv7 | Peter Crosthwaite | 2015-06-19 | 1 | -0/+6 |
* | target-arm/helper.c: define MPUIR register | Peter Crosthwaite | 2015-06-19 | 1 | -0/+18 |
* | target-arm: Do not reset sysregs marked as ALIAS | Sergey Fedorov | 2015-06-19 | 1 | -1/+1 |
* | target-arm: Add the Cortex-M4 CPU | Aurelio C. Remonda | 2015-06-19 | 1 | -0/+11 |
* | arm: Add has-mpu property | Peter Crosthwaite | 2015-06-15 | 1 | -0/+13 |
* | target-arm: Add the THUMB_DSP feature | Aurelio C. Remonda | 2015-06-15 | 1 | -0/+4 |
* | target-arm: Use the kernel's idea of MPIDR if we're using KVM | Pavel Fedin | 2015-06-15 | 1 | -0/+12 |
* | target-arm: Update interrupt handling to use target EL | Greg Bellows | 2015-05-29 | 1 | -20/+41 |
* | target-arm: Move setting of exception info into tlb_fill | Peter Maydell | 2015-05-29 | 1 | -0/+17 |
* | target-arm: Adjust id_aa64pfr0 when has_el3 CPU property disabled | Sergey Fedorov | 2015-04-26 | 1 | -1/+2 |
* | target-arm: rename c1_coproc to cpacr_el1 | Sergey Fedorov | 2015-04-26 | 1 | -2/+2 |
* | target-arm: Add CPU property to disable AArch64 | Greg Bellows | 2015-02-13 | 1 | -1/+4 |
* | target-arm: Guest cpu endianness determination for virtio KVM ARM/ARM64 | Pranavkumar Sawargaonkar | 2015-02-05 | 1 | -0/+24 |
* | target-arm: Change reset to highest available EL | Greg Bellows | 2015-02-05 | 1 | -1/+8 |
* | target-arm: add cpu feature EL3 to CPUs with Security Extensions | Fabian Aggeler | 2014-12-23 | 1 | -0/+4 |
* | target-arm: Add ARMCPU secure property | Greg Bellows | 2014-12-23 | 1 | -0/+23 |
* | target-arm: Add feature unset function | Greg Bellows | 2014-12-23 | 1 | -0/+5 |
* | target-arm: make IFAR/DFAR banked | Fabian Aggeler | 2014-12-11 | 1 | -1/+1 |
* | target-arm: add SCTLR_EL3 and make SCTLR banked | Fabian Aggeler | 2014-12-11 | 1 | -2/+6 |
* | target-arm: Separate out M profile cpu_exec_interrupt handling | Peter Maydell | 2014-11-04 | 1 | -10/+39 |
* | target-arm: Correct sense of the DCZID DZP bit | Peter Maydell | 2014-10-24 | 1 | -2/+2 |
* | target-arm: add emulation of PSCI calls for system emulation | Rob Herring | 2014-10-24 | 1 | -3/+7 |
* | target-arm: do not set do_interrupt handlers for ARM and AArch64 user modes | Rob Herring | 2014-10-24 | 1 | -1/+1 |