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path: root/target-arm/helper-a64.c
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* cpu: move exec-all.h inclusion out of cpu.hPaolo Bonzini2016-05-191-0/+1
* target-arm: Move aarch64_cpu_do_interrupt() to helper.cPeter Maydell2016-01-211-104/+0Star
* target-arm: Clean up includesPeter Maydell2016-01-181-0/+1
* target-arm: kvm - re-inject guest debug exceptionsAlex Bennée2015-12-171-2/+10
* target-arm: Use new revbit functionsRichard Henderson2015-09-151-14/+1Star
* target-arm: Log the target EL when taking exceptionsEdgar E. Iglesias2015-09-081-1/+2
* target-arm: Wire up HLT 0xf000 as the A64 semihosting instructionPeter Maydell2015-09-071-0/+6
* target-arm: A64: Print ELR when taking exceptionsSoren Brinkmann2015-06-261-0/+2
* target-arm: Update interrupt handling to use target ELGreg Bellows2015-05-291-1/+1
* target-arm: Store SPSR_EL1 state in banked_spsr[1] (SPSR_svc)Peter Maydell2015-04-011-1/+1
* target-arm: Add 32/64-bit register syncGreg Bellows2015-02-131-4/+1Star
* target-arm: Squash input denormals in FRECPS and FRSQRTSPeter Maydell2015-02-051-0/+12
* Fix FMULX not squashing denormalized inputs when FZ is set.Xiangyu Hu2015-02-051-0/+6
* target-arm: rename arm_current_pl to arm_current_elGreg Bellows2014-10-241-3/+3
* target-arm: add emulation of PSCI calls for system emulationRob Herring2014-10-241-0/+6
* target-arm: do not set do_interrupt handlers for ARM and AArch64 user modesRob Herring2014-10-241-0/+3
* target-arm: Add support for VIRQ and VFIQEdgar E. Iglesias2014-09-291-0/+2
* target-arm: A64: Emulate the SMC insnEdgar E. Iglesias2014-09-291-0/+1
* target-arm: Add a Hypervisor Trap exception typeEdgar E. Iglesias2014-09-291-0/+1
* target-arm: A64: Emulate the HVC insnEdgar E. Iglesias2014-09-291-0/+1
* target-arm: A64: Correct updates to FAR and ESR on exceptionsEdgar E. Iglesias2014-09-291-4/+3Star
* target-arm: A64: Refactor aarch64_cpu_do_interruptEdgar E. Iglesias2014-09-291-11/+13
* target-arm: Make far_el1 an arrayEdgar E. Iglesias2014-08-041-2/+2
* target-arm: A64: Respect SPSEL when taking exceptionsEdgar E. Iglesias2014-08-041-2/+2
* target-arm: A64: Implement CRC instructionsPeter Maydell2014-06-091-0/+30
* target-arm: add support for v8 VMULL.P64 instructionPeter Maydell2014-06-091-30/+0Star
* tcg: Invert the inclusion of helper.hRichard Henderson2014-05-281-1/+1
* target-arm: A64: Introduce aarch64_banked_spsr_index()Edgar E. Iglesias2014-05-271-1/+1
* target-arm: c12_vbar -> vbar_el[]Edgar E. Iglesias2014-05-271-1/+1
* target-arm: Make esr_el1 an arrayEdgar E. Iglesias2014-05-271-2/+2
* target-arm: Make elr_el1 an arrayEdgar E. Iglesias2014-05-271-2/+2
* target-arm: Implement AArch64 EL1 exception handlingRob Herring2014-04-171-0/+76
* target-arm: A64: Implement FCVTXNPeter Maydell2014-03-171-0/+23
* target-arm: A64: Add FRECPX (reciprocal exponent)Alex Bennée2014-03-171-0/+59
* target-arm: A64: Implement SADDLP, UADDLP, SADALP, UADALPPeter Maydell2014-03-171-0/+61
* target-arm: A64: Add remaining CLS/Z vector opsAlex Bennée2014-03-171-0/+5
* target-arm: A64: Implement PMULL instructionPeter Maydell2014-03-171-0/+30
* target-arm: A64: Implement remaining 3-same instructionsPeter Maydell2014-02-201-0/+60
* target-arm: A64: Implement SIMD FP compare and set insnsAlex Bennée2014-02-201-0/+19
* target-arm: A64: Implement plain vector SIMD indexed element insnsPeter Maydell2014-02-201-0/+26
* target-arm: A64: Add SIMD TBL/TBLXMichael Matz2014-01-311-0/+31
* target-arm: A64: Add support for floating point compareClaudio Fontana2014-01-081-0/+45
* target-arm: A64: add support for 1-src CLS insnClaudio Fontana2013-12-171-0/+10
* target-arm: A64: add support for 1-src RBIT insnAlexander Graf2013-12-171-0/+18
* target-arm: A64: add support for 1-src data processing and CLZClaudio Fontana2013-12-171-0/+5
* target-arm: A64: add support for 2-src data processing and DIVAlexander Graf2013-12-171-0/+21
* target-arm: A64: add stubs for a64 specific helpersAlexander Graf2013-12-171-0/+25
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