summaryrefslogtreecommitdiffstats
path: root/target-arm/translate-a64.c
Commit message (Expand)AuthorAgeFilesLines
* Move target-* CPU file into a target/ folderThomas Huth2016-12-201-11430/+0Star
* target-arm/translate-a64: fix gen_load_exclusiveAlex Bennée2016-12-051-23/+19Star
* log: Add locking to large logging blocksRichard Henderson2016-11-011-0/+2
* target-arm: emulate aarch64's LL/SC using cmpxchg helpersEmilio G. Cota2016-10-261-58/+48Star
* target-arm: Comments added to identify cases in a switchThomas Hanson2016-10-171-3/+3
* target-arm: Code changes to implement overwrite of tag field on PC loadThomas Hanson2016-10-171-5/+77
* target-arm: Infrastucture changes to enable handling of tagged address loadin...Thomas Hanson2016-10-171-0/+2
* target-arm: A64: Fix decoding of iss_sf in disas_ld_litEdgar E. Iglesias2016-10-041-1/+1
* target-aarch64: Generate fences for aarch64Pranith Kumar2016-09-161-1/+26
* target-arm: A64: Create Instruction Syndromes for Data AbortsEdgar E. Iglesias2016-06-061-22/+118
* cpu: move exec-all.h inclusion out of cpu.hPaolo Bonzini2016-05-191-0/+1
* tcg: Allow goto_tb to any target PC in user modeSergey Fedorov2016-05-131-0/+2
* target-arm/translate-a64.c: Unify some of the ldst_reg decodingEdgar E. Iglesias2016-05-121-18/+23
* target-arm/translate-a64.c: Use extract32 in disas_ldst_reg_imm9Edgar E. Iglesias2016-05-121-2/+2
* target-arm: dfilter support for in_asmAlex Bennée2016-03-221-1/+2
* target-arm: introduce tbflag for endiannessPeter Crosthwaite2016-03-041-1/+1
* target-arm: a64: Add endianness supportPeter Crosthwaite2016-03-041-19/+30
* target-arm: introduce disas flag for endiannessPaolo Bonzini2016-03-041-0/+1
* target-arm: implement SCTLR.B, drop bswap_codePaolo Bonzini2016-03-041-3/+3
* target-arm: Add isread parameter to CPAccessFnsPeter Maydell2016-02-111-2/+4
* tcg: Change tcg_global_mem_new_* to take a TCGv_ptrRichard Henderson2016-02-091-3/+3
* log: do not unnecessarily include qom/cpu.hPaolo Bonzini2016-02-031-0/+1
* target-arm: Clean up includesPeter Maydell2016-01-181-5/+1Star
* target-arm/translate-a64.c: Correct unallocated checks for ldst_exclPeter Maydell2015-11-241-13/+2Star
* target-arm: Update PC before calling gen_helper_check_breakpoints()Sergey Fedorov2015-11-121-0/+1
* target-arm: Report S/NS status in the CPU debug logsPeter Maydell2015-11-031-1/+10
* target-arm: Bring AArch64 debug CPU display of PSTATE into line with AArch32Peter Maydell2015-11-031-3/+5
* target-*: Advance pc after recognizing a breakpointRichard Henderson2015-10-281-2/+5
* target-arm: Fix CPU breakpoint handlingSergey Fedorov2015-10-161-5/+12
* target-arm: Break the TB after ISB to execute self-modified code correctlySergey Sorokin2015-10-161-1/+7
* tcg: Remove gen_intermediate_code_pcRichard Henderson2015-10-071-27/+3Star
* tcg: Add TCG_MAX_INSNSRichard Henderson2015-10-071-0/+3
* target-arm: Add condexec state to insn_startRichard Henderson2015-10-071-1/+1
* target-*: Introduce and use cpu_breakpoint_testRichard Henderson2015-10-071-13/+13
* target-*: Increment num_insns immediately after tcg_gen_insn_startRichard Henderson2015-10-071-3/+3
* target-*: Unconditionally emit tcg_gen_insn_startRichard Henderson2015-10-071-4/+1Star
* tcg: Rename debug_insn_start to insn_startRichard Henderson2015-10-071-1/+1
* target-arm: Use tcg_gen_extrh_i64_i32Richard Henderson2015-09-141-25/+9Star
* target-arm: Recognize RORRichard Henderson2015-09-141-12/+21
* target-arm: Eliminate unnecessary zero-extend in disas_bitfieldRichard Henderson2015-09-141-1/+5
* target-arm: Recognize UXTB, UXTH, LSR, LSLRichard Henderson2015-09-141-0/+17
* target-arm: Recognize SXTB, SXTH, SXTW, ASRRichard Henderson2015-09-141-1/+23
* target-arm: Implement fcsel with movcondRichard Henderson2015-09-141-28/+17Star
* target-arm: Implement ccmp branchlessRichard Henderson2015-09-141-16/+58
* target-arm: Use setcond and movcond for cselRichard Henderson2015-09-141-36/+49
* target-arm: Share all common TCG temporariesRichard Henderson2015-09-141-22/+0Star
* target-arm: Fix default_exception_el() function for the case when EL3 is not ...Sergey Sorokin2015-09-081-1/+5
* target-arm: Wire up HLT 0xf000 as the A64 semihosting instructionPeter Maydell2015-09-071-2/+22
* tcg: Remove tcg_gen_trunc_i64_i32Richard Henderson2015-08-241-30/+30
* target-arm: Split DISAS_YIELD from DISAS_WFEPeter Maydell2015-07-061-0/+6
generated by cgit v1.2.3-55-g7522 (git 2.39.0) at 2024-07-18 12:22:17 +0200