summaryrefslogtreecommitdiffstats
path: root/target-arm/translate.c
Commit message (Expand)AuthorAgeFilesLines
* cpu: move exec-all.h inclusion out of cpu.hPaolo Bonzini2016-05-191-0/+1
* tcg: Allow goto_tb to any target PC in user modeSergey Fedorov2016-05-131-6/+12
* tcg: Clean up direct block chaining safety checksSergey Fedorov2016-05-131-1/+2
* target-arm: dfilter support for in_asmAlex Bennée2016-03-221-1/+2
* target-arm: Implement MRS (banked) and MSR (banked) instructionsPeter Maydell2016-03-161-3/+243
* target-arm: Only trap SRS from S-EL1 if specified mode is MONRalf-Philipp Weinmann2016-03-041-1/+2
* target-arm: implement BE32 mode in system emulationPaolo Bonzini2016-03-041-15/+71
* target-arm: implement setendPaolo Bonzini2016-03-041-8/+6Star
* target-arm: introduce tbflag for endiannessPeter Crosthwaite2016-03-041-1/+1
* target-arm: introduce disas flag for endiannessPaolo Bonzini2016-03-041-15/+24
* target-arm: pass DisasContext to gen_aa32_ld*/st*Paolo Bonzini2016-03-041-128/+142
* target-arm: implement SCTLR.B, drop bswap_codePaolo Bonzini2016-03-041-8/+8
* tcg: Add type for vCPU pointersLluís Vilanova2016-03-011-1/+1
* target-arm: Give CPSR setting on 32-bit exception return its own helperPeter Maydell2016-02-261-3/+3
* target-arm: UNDEF in the UNPREDICTABLE SRS-from-System casePeter Maydell2016-02-181-4/+5
* target-arm: Clean up trap/undef handling of SRSPeter Maydell2016-02-181-5/+61
* target-arm: Fix IL bit reported for Thumb VFP and Neon trapsPeter Maydell2016-02-111-3/+3
* target-arm: Fix IL bit reported for Thumb coprocessor trapsPeter Maydell2016-02-111-4/+4
* target-arm: Add isread parameter to CPAccessFnsPeter Maydell2016-02-111-2/+5
* tcg: Change tcg_global_mem_new_* to take a TCGv_ptrRichard Henderson2016-02-091-9/+9
* tcg: Remove lingering references to gen_opc_bufRichard Henderson2016-02-091-2/+1Star
* log: do not unnecessarily include qom/cpu.hPaolo Bonzini2016-02-031-0/+1
* target-arm: Clean up includesPeter Maydell2016-01-181-5/+1Star
* target-arm: Fix and improve AA32 singlestep translation completion codeSergey Fedorov2015-12-171-34/+31Star
* target-arm: raise exception on misaligned LDREX operandsAndrew Baumann2015-12-171-4/+7
* target-arm: Update condexec before arch BP check in AA32 translationSergey Fedorov2015-11-191-0/+1
* target-arm: Update condexec before CP access check in AA32 translationSergey Fedorov2015-11-191-0/+1
* target-arm: Update PC before calling gen_helper_check_breakpoints()Sergey Fedorov2015-11-121-0/+1
* target-arm: Clean up DISAS_UPDATE usage in AArch32 translation codeSergey Fedorov2015-11-101-11/+14
* target-arm: Report S/NS status in the CPU debug logsPeter Maydell2015-11-031-1/+11
* target-*: Advance pc after recognizing a breakpointRichard Henderson2015-10-281-2/+5
* target-arm/translate.c: Handle non-executable page-straddling Thumb insnsPeter Maydell2015-10-271-1/+44
* target-arm: Fix CPU breakpoint handlingSergey Fedorov2015-10-161-5/+14
* target-arm: Break the TB after ISB to execute self-modified code correctlySergey Sorokin2015-10-161-2/+15
* tcg: Remove gen_intermediate_code_pcRichard Henderson2015-10-071-45/+9Star
* tcg: Pass data argument to restore_state_to_opcRichard Henderson2015-10-071-4/+5
* tcg: Add TCG_MAX_INSNSRichard Henderson2015-10-071-1/+5
* target-arm: Add condexec state to insn_startRichard Henderson2015-10-071-1/+2
* target-*: Introduce and use cpu_breakpoint_testRichard Henderson2015-10-071-15/+16
* target-*: Increment num_insns immediately after tcg_gen_insn_startRichard Henderson2015-10-071-3/+4
* target-*: Unconditionally emit tcg_gen_insn_startRichard Henderson2015-10-071-4/+1Star
* tcg: Rename debug_insn_start to insn_startRichard Henderson2015-10-071-1/+1
* target-arm: Handle always condition codes within arm_test_ccRichard Henderson2015-09-141-0/+9
* target-arm: Introduce DisasCompareRichard Henderson2015-09-141-46/+69
* target-arm: Share all common TCG temporariesRichard Henderson2015-09-141-5/+5
* maint: remove / fix many doubled wordsDaniel P. Berrange2015-09-111-1/+1
* target-arm: Fix default_exception_el() function for the case when EL3 is not ...Sergey Sorokin2015-09-081-1/+5
* tcg: Remove tcg_gen_trunc_i64_i32Richard Henderson2015-08-241-23/+23
* target-arm: Implement YIELD insn to yield in ARM and Thumb translatorsPeter Maydell2015-07-061-0/+7
* disas: Remove uses of CPU envPeter Crosthwaite2015-06-221-1/+1
generated by cgit v1.2.3-55-g7522 (git 2.39.0) at 2024-12-22 17:54:08 +0100