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path: root/target-arm/translate.c
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* disas: Remove uses of CPU envPeter Crosthwaite2015-06-221-1/+1
* target-arm: Correct "preferred return address" for cpreg access exceptionsPeter Maydell2015-06-151-1/+1
* target-arm: Add the THUMB_DSP featureAurelio C. Remonda2015-06-151-10/+102
* target-arm: Avoid buffer overrun on UNPREDICTABLE ldrd/strdPeter Maydell2015-05-291-24/+32
* target-arm: Don't halt on WFI unless we don't have any workPeter Maydell2015-05-291-0/+4
* target-arm: Extend FP checks to use an ELGreg Bellows2015-05-291-10/+7Star
* target-arm: Add exception target el infrastructureGreg Bellows2015-05-291-23/+42
* target-arm: Fix handling of STM (user) with r15 in register listPeter Maydell2015-03-161-6/+12
* tcg: Change translator-side labels to a pointerRichard Henderson2015-03-131-4/+4
* tcg: Introduce tcg_op_buf_count and tcg_op_buf_fullRichard Henderson2015-02-131-6/+3Star
* tcg: Move emit of INDEX_op_end into gen_tb_endRichard Henderson2015-02-131-1/+0Star
* target-arm: Use correct mmu_idx for unprivileged loads and storesPeter Maydell2015-02-051-2/+24
* target-arm: Define correct mmu_idx values and pass them in TB flagsPeter Maydell2015-02-051-2/+3
* target-arm: check that LSB <= MSB in BFI instructionKirill Batuzov2015-02-051-0/+4
* gen-icount: check cflags instead of use_icount globalPaolo Bonzini2015-01-031-1/+1
* translate: check cflags instead of use_icount globalPaolo Bonzini2015-01-031-2/+2
* target-arm: add secure state bit to CPREG hashPeter Maydell2014-12-111-5/+9
* target-arm: add non-secure Translation Block flagSergey Fedorov2014-12-111-0/+1
* target-arm/translate.c: Don't pass CPUARMState * to disas_arm_insn()Peter Maydell2014-11-041-6/+5Star
* target-arm/translate.c: Don't pass CPUARMState around in the decoderPeter Maydell2014-11-041-44/+50
* target-arm/translate.c: Don't use IS_M()Peter Maydell2014-11-041-8/+11
* target-arm/translate.c: Use arm_dc_feature() rather than arm_feature()Peter Maydell2014-11-041-60/+80
* target-arm/translate.c: Use arm_dc_feature() in ENABLE_ARCH_ macrosPeter Maydell2014-11-041-8/+8
* target-arm: rename arm_current_pl to arm_current_elGreg Bellows2014-10-241-2/+2
* target-arm: correctly UNDEF writes to FPINST/FPINST2 from EL0Peter Maydell2014-10-241-0/+3
* target-arm: Add support for A32 and T32 HVC and SMC insnsPeter Maydell2014-10-241-11/+92
* target-arm: Don't handle c15_cpar changes via tb_flush()Peter Maydell2014-09-291-19/+21
* target-arm: Implement ARMv8 single-stepping for AArch32 codePeter Maydell2014-08-191-2/+74
* target-arm: Don't allow AArch32 to access RES0 CPSR bitsPeter Maydell2014-08-191-6/+7
* trace: [tcg] Include TCG-tracing header on all targetsLluís Vilanova2014-08-121-0/+3
* target-arm: Delete unused iwmmxt_msadb helperPeter Maydell2014-06-091-2/+0Star
* target-arm: A32/T32: Mask CRC value in calling code, not helperPeter Maydell2014-06-091-0/+10
* target-arm: add support for v8 VMULL.P64 instructionPeter Maydell2014-06-091-1/+25
* target-arm: Allow 3reg_wide undefreq to encode more bad size optionsPeter Maydell2014-06-091-12/+12
* target-arm: add support for v8 SHA1 and SHA256 instructionsArd Biesheuvel2014-06-091-0/+84
* target-arm: move arm_*_code to a separate filePaolo Bonzini2014-06-051-0/+1
* tcg: Invert the inclusion of helper.hRichard Henderson2014-05-281-3/+2Star
* target-arm: Add SPSR entries for EL2/HYP and EL3/MONEdgar E. Iglesias2014-05-271-2/+2
* target-arm: A32: Use get_mem_index for load/storesEdgar E. Iglesias2014-05-271-106/+106
* target-arm/translate.c: Use get_mem_index() for SRS memory accessesPeter Maydell2014-05-271-2/+2
* target-arm/translate.c: Clean up mmu index handling for ldrt/strtPeter Maydell2014-05-271-12/+17
* arm: translate.c: Fix smlald InstructionPeter Crosthwaite2014-04-171-11/+23
* target-arm: Dump 32-bit CPU state if 64 bit CPU is in AArch32Peter Maydell2014-04-171-0/+5
* target-arm: Implement ARMv8 MVFR registersPeter Maydell2014-04-171-2/+8
* target-arm: Fix VFP enables for AArch32 EL0 under AArch64 EL1Peter Maydell2014-04-171-0/+31
* target-arm: Add support for generating exceptions with syndrome informationPeter Maydell2014-04-171-38/+65
* target-arm: Provide correct syndrome information for cpreg access trapsPeter Maydell2014-04-171-1/+44
* target-arm: Split out private-to-target functions into internals.hPeter Maydell2014-04-171-0/+1
* target-arm: A64: Add [UF]RSQRTE (reciprocal root estimate)Alex Bennée2014-03-171-2/+10
* target-arm: A64: Implement AdvSIMD reciprocal estimate insns URECPE, FRECPEAlex Bennée2014-03-171-2/+10
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