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* arm: fix compile on bigendian hostAlexey Kardashevskiy2014-01-121-1/+1
* target-arm: A64: Add support for FCVT between half, single and doublePeter Maydell2014-01-083-1/+96
* target-arm: A64: Add 1-source 32-to-32 and 64-to-64 FP instructionsPeter Maydell2014-01-083-1/+191
* target-arm: A64: Add floating-point<->integer conversion instructionsWill Newton2014-01-081-3/+20
* target-arm: A64: Add floating-point<->fixed-point instructionsAlexander Graf2014-01-083-1/+200
* target-arm: A64: Add extra VFP fixed point conversion helpersWill Newton2014-01-082-1/+26
* target-arm: Ignore most exceptions from scalbn when doing fixpoint conversionPeter Maydell2014-01-081-0/+9
* target-arm: Rename A32 VFP conversion helpersWill Newton2014-01-083-24/+35
* target-arm: Prepare VFP_CONV_FIX helpers for A64 usesWill Newton2014-01-081-14/+14
* target-arm: fix build with gcc 4.8.2Michael S. Tsirkin2014-01-081-0/+6
* target-arm: remove raw_read|write duplicationPeter Crosthwaite2014-01-081-10/+2Star
* target-arm: use c13_context field for CONTEXTIDRSergey Fedorov2014-01-081-1/+1
* target-arm: Give the FPSCR rounding modes namesAlexander Graf2014-01-082-4/+13
* target-arm: A64: Add support for floating point cond selectClaudio Fontana2014-01-081-1/+44
* target-arm: A64: Add support for floating point conditional compareClaudio Fontana2014-01-081-1/+34
* target-arm: A64: Add support for floating point compareClaudio Fontana2014-01-083-1/+113
* target-arm: A64: Add fmov (scalar, immediate) instructionAlexander Graf2014-01-081-1/+31
* target-arm: A64: Add "Floating-point data-processing (3 source)" insnsAlexander Graf2014-01-081-1/+94
* target-arm: A64: Add "Floating-point data-processing (2 source)" insnsAlexander Graf2014-01-081-1/+181
* target-arm: Use VFP_BINOP macro for min, max, minnum, maxnumPeter Maydell2014-01-084-52/+20Star
* target-arm: A64: Fix vector register access on bigendian hostsPeter Maydell2014-01-081-34/+35
* target-arm: A64: Add support for dumping AArch64 VFP register stateAlexander Graf2014-01-081-0/+16
* target-arm: A64: support for ld/st/cl exclusiveMichael Matz2014-01-081-3/+153
* target-arm: Widen exclusive-access support struct fields to 64 bitsPeter Maydell2014-01-083-36/+49
* target-arm: aarch64: add support for ld litAlexander Graf2014-01-081-2/+45
* target-arm: A64: add support for conditional compare insnsClaudio Fontana2014-01-081-13/+60
* target-arm: A64: add support for add/sub with carryClaudio Fontana2014-01-081-2/+103
* target-arm: Widen thread-local register state fields to 64 bitsPeter Maydell2014-01-072-10/+30
* target-arm: A64: Implement minimal set of EL0-visible sysregsPeter Maydell2014-01-073-1/+115
* target-arm: A64: Implement MRS/MSR/SYS/SYSLPeter Maydell2014-01-071-30/+82
* target-arm: Remove ARMCPU/CPUARMState from cpregs APIs used by decoderPeter Maydell2014-01-075-12/+17
* target-arm: Update generic cpreg code for AArch64Peter Maydell2014-01-043-9/+211
* target-arm: Pull "add one cpreg to hashtable" into its own functionPeter Maydell2014-01-041-42/+52
* target-arm: A64: implement FMOVPeter Maydell2013-12-241-1/+85
* target-arm: A64: Add decoder skeleton for FP instructionsPeter Maydell2013-12-241-1/+169
* target-arm: A64: implement SVC, BRKAlexander Graf2013-12-241-2/+49
* target-arm: A64: add support for 3 src data proc insnsAlexander Graf2013-12-241-2/+95
* target-arm: A64: add support for move wide instructionsAlex Bennée2013-12-241-2/+49
* target-arm: A64: add support for add, addi, sub, subiAlex Bennée2013-12-241-6/+286
* target-arm: A64: add support for ld/st with indexAlex Bennée2013-12-241-1/+124
* target-arm: A64: add support for ld/st with reg offsetAlex Bennée2013-12-241-1/+143
* target-arm: A64: add support for ld/st unsigned immAlex Bennée2013-12-241-1/+88
* target-arm: A64: add support for ld/st pairPeter Maydell2013-12-241-2/+277
* target-arm: A64: add support for logical (immediate) insnsAlexander Graf2013-12-171-2/+173
* target-arm: A64: add support for 1-src CLS insnClaudio Fontana2013-12-173-1/+31
* target-arm: A64: add support for bitfield insnsClaudio Fontana2013-12-171-2/+54
* target-arm: A64: add support for 1-src REV insnsClaudio Fontana2013-12-171-1/+72
* target-arm: A64: add support for 1-src RBIT insnAlexander Graf2013-12-173-0/+39
* target-arm: A64: add support for 1-src data processing and CLZClaudio Fontana2013-12-173-2/+56
* target-arm: A64: add support for 2-src shift reg insnsAlexander Graf2013-12-171-0/+22
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