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* target-arm: Implement pmccfiltr_write functionAlistair Francis2014-08-291-0/+9
* target-arm: Remove old code and replace with new functionsAlistair Francis2014-08-291-23/+4Star
* target-arm: Implement pmccntr_sync functionAlistair Francis2014-08-292-0/+34
* target-arm: Add arm_ccnt_enabled functionAlistair Francis2014-08-291-0/+12
* target-arm: Implement PMCCNTR_EL0 and related registersAlistair Francis2014-08-292-8/+42
* arm: Implement PMCCNTR 32b read-modify-writePeter Crosthwaite2014-08-291-1/+10
* target-arm: Make the ARM PMCCNTR register 64-bitAlistair Francis2014-08-292-11/+10Star
* target-arm: Correct Cortex-A57 ISAR5 and AA64ISAR0 ID register valuesPeter Maydell2014-08-291-1/+2
* target-arm: Fix regression that disabled VFP for ARMv5 CPUsPeter Maydell2014-08-291-1/+8
* arm: cortex-a9: Fix cache-line size and associativityPeter Crosthwaite2014-08-191-2/+2
* arm/virt: Use PSCI v0.2 function IDs in the DT when KVM uses PSCI v0.2Christoffer Dall2014-08-191-0/+27
* target-arm: Rename QEMU PSCI v0.1 definitionsChristoffer Dall2014-08-191-11/+11
* target-arm: Implement MDSCR_EL1 as having statePeter Maydell2014-08-191-1/+3
* target-arm: Implement ARMv8 single-stepping for AArch32 codePeter Maydell2014-08-192-2/+95
* target-arm: Implement ARMv8 single-step handling for A64 codePeter Maydell2014-08-196-5/+131
* target-arm: A64: Avoid duplicate exit_tb(0) in non-linked goto_tbPeter Maydell2014-08-191-2/+3
* target-arm: Set PSTATE.SS correctly on exception return from AArch64Peter Maydell2014-08-192-0/+81
* target-arm: Correctly handle PSTATE.SS when taking exception to AArch32Peter Maydell2014-08-191-0/+4
* target-arm: Don't allow AArch32 to access RES0 CPSR bitsPeter Maydell2014-08-193-9/+18
* target-arm: Adjust debug ID registers per-CPUPeter Maydell2014-08-194-7/+31
* target-arm: Provide both 32 and 64 bit versions of debug registersPeter Maydell2014-08-191-14/+20
* target-arm: Allow STATE_BOTH reginfo descriptions for more than cp14Peter Maydell2014-08-191-3/+8
* target-arm: Collect up the debug cp register definitionsPeter Maydell2014-08-191-32/+53
* target-arm: Fix return address for A64 BRK instructionsPeter Maydell2014-08-191-1/+1
* trace: [tcg] Include TCG-tracing header on all targetsLluís Vilanova2014-08-122-0/+5
* target-arm: A64: fix TLB flush instructionsAlex Bennée2014-08-041-2/+8
* target-arm: don't hardcode mask values in arm_cpu_handle_mmu_faultAlex Bennée2014-08-041-2/+2
* target-arm: Fix bit test in sp_el0_accessStefan Weil2014-08-041-1/+1
* target-arm: Add FAR_EL2 and 3Edgar E. Iglesias2014-08-042-1/+7
* target-arm: Add ESR_EL2 and 3Edgar E. Iglesias2014-08-042-1/+9
* target-arm: Make far_el1 an arrayEdgar E. Iglesias2014-08-044-10/+10
* target-arm: A64: Respect SPSEL when taking exceptionsEdgar E. Iglesias2014-08-041-2/+2
* target-arm: A64: Respect SPSEL in ERET SP restoreEdgar E. Iglesias2014-08-041-1/+1
* target-arm: A64: Break out aarch64_save/restore_spEdgar E. Iglesias2014-08-043-24/+24
* target-arm: Implement vCPU reset via KVM_ARM_VCPU_INIT for 32-bit CPUsPeter Maydell2014-07-082-18/+5Star
* Fix new typos (found by codespell)Stefan Weil2014-06-241-1/+1
* target-arm: Introduce per-CPU field for PSCI versionPranavkumar Sawargaonkar2014-06-194-0/+9
* target-arm: Implement kvm_arch_reset_vcpu() for KVM ARM64Pranavkumar Sawargaonkar2014-06-191-0/+4
* target-arm: Enable KVM_ARM_VCPU_PSCI_0_2 feature when possiblePranavkumar Sawargaonkar2014-06-192-0/+6
* target-arm: Common kvm_arm_vcpu_init() for KVM ARM and KVM ARM64Pranavkumar Sawargaonkar2014-06-195-12/+44
* target-arm/translate-a64.c: Fix dead ?: in handle_simd_shift_fpint_conv()Peter Maydell2014-06-191-1/+1
* target-arm/translate-a64.c: Remove dead ?: in disas_simd_3same_int()Peter Maydell2014-06-191-1/+2
* target-arm: Add ULL suffix to calculation of page sizePeter Maydell2014-06-191-1/+1
* target-arm: implement PD0/PD1 bits for TTBCRFabian Aggeler2014-06-192-18/+60
* target-arm: Use Common Tables in AES InstructionsTom Musta2014-06-161-75/+4Star
* target-arm: Delete unused iwmmxt_msadb helperPeter Maydell2014-06-093-13/+0Star
* target-arm: Fix errors in writes to generic timer control registersPeter Maydell2014-06-091-3/+3
* target-arm: A64: Implement two-register SHA instructionsPeter Maydell2014-06-091-1/+44
* target-arm: A64: Implement 3-register SHA instructionsPeter Maydell2014-06-091-1/+58
* target-arm: A64: Implement AES instructionsPeter Maydell2014-06-091-1/+50
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