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* virtio: move bi-endian target support to a single locationGreg Kurz2016-06-071-2/+0Star
* target-arm: Fix TTBR selecting logic on AArch32 Stage 2 translationSergey Sorokin2016-06-061-16/+22
* target-arm: Don't try to set ESR IL bit in arm_cpu_do_interrupt_aarch64()Peter Maydell2016-06-061-3/+0Star
* target-arm: Set IL bit in syndromes for insn abort, watchpoint, swstepPeter Maydell2016-06-061-3/+3
* target-arm: A64: Create Instruction Syndromes for Data AbortsEdgar E. Iglesias2016-06-065-30/+180
* target-arm: Add the HSTR_EL2 registerAlistair Francis2016-06-062-0/+8
* cpu: move exec-all.h inclusion out of cpu.hPaolo Bonzini2016-05-1910-2/+9
* hw: explicitly include qemu/log.hPaolo Bonzini2016-05-193-0/+3
* arm: move arm_log_exception into .c filePaolo Bonzini2016-05-192-15/+15
* qemu-common: push cpu.h inclusion out of qemu-common.hPaolo Bonzini2016-05-196-2/+7
* hw: move CPU state serialization to migration/cpu.hPaolo Bonzini2016-05-191-0/+1
* target-arm: make cpu-qom.h not target specificPaolo Bonzini2016-05-192-178/+179
* cpu: make cpu-qom.h only include-able from cpu.hPaolo Bonzini2016-05-191-1/+0Star
* tcg: Allow goto_tb to any target PC in user modeSergey Fedorov2016-05-132-6/+14
* tcg: Clean up direct block chaining safety checksSergey Fedorov2016-05-131-1/+2
* tb: consistently use uint32_t for tb->flagsEmilio G. Cota2016-05-131-1/+1
* target-arm: Avoid unnecessary TLB flush on TCR_EL2, TCR_EL3 writesPeter Maydell2016-05-121-4/+8
* ARM: Factor out ARM on/off PSCI control functionsJean-Christophe DUBOIS2016-05-124-63/+307
* target-arm/translate-a64.c: Unify some of the ldst_reg decodingEdgar E. Iglesias2016-05-121-18/+23
* target-arm/translate-a64.c: Use extract32 in disas_ldst_reg_imm9Edgar E. Iglesias2016-05-121-2/+2
* target-arm: Split data abort syndrome generatorPeter Maydell2016-05-122-5/+25
* target-arm: Fix descriptor address masking in ARM address translationSergey Sorokin2016-05-121-18/+11Star
* target-arm: Stage 2 permission fault was fixed in AArch32 stateSergey Sorokin2016-05-121-1/+3
* target-arm: Make the 64-bit version of VTCR do the migrationPeter Maydell2016-04-041-1/+5
* target-arm: Remove incorrect ALIAS tags from ESR_EL2 and ESR_EL3Peter Maydell2016-04-041-2/+0Star
* target-arm: Correctly reset SCTLR_EL3 for 64-bit CPUsPeter Maydell2016-04-041-10/+13
* arm: implement query-gic-capabilitiesPeter Xu2016-03-301-1/+57
* arm: enhance kvm_arm_create_scratch_host_vcpuPeter Xu2016-03-302-3/+18
* arm: qmp: add query-gic-capabilities interfacePeter Xu2016-03-302-1/+29
* target-arm: dfilter support for in_asmAlex Bennée2016-03-222-2/+4
* util: move declarations out of qemu-common.hVeronia Bahaa2016-03-221-0/+1
* include/qemu/osdep.h: Don't include qapi/error.hMarkus Armbruster2016-03-222-0/+2
* target-arm: Fix translation level on early translation faultsSergey Sorokin2016-03-161-10/+12
* target-arm: Implement MRS (banked) and MSR (banked) instructionsPeter Maydell2016-03-163-3/+366
* target-arm: Only trap SRS from S-EL1 if specified mode is MONRalf-Philipp Weinmann2016-03-041-1/+2
* target-arm: implement BE32 mode in system emulationPaolo Bonzini2016-03-042-18/+73
* target-arm: implement setendPaolo Bonzini2016-03-043-8/+12
* target-arm: introduce tbflag for endiannessPeter Crosthwaite2016-03-043-2/+9
* target-arm: a64: Add endianness supportPeter Crosthwaite2016-03-041-19/+30
* target-arm: introduce disas flag for endiannessPaolo Bonzini2016-03-043-15/+26
* target-arm: pass DisasContext to gen_aa32_ld*/st*Paolo Bonzini2016-03-041-128/+142
* target-arm: implement SCTLR.EEPeter Crosthwaite2016-03-041-2/+21
* linux-user: arm: handle CPSR.E correctly in strex emulationPaolo Bonzini2016-03-041-0/+11
* arm: cpu: handle BE32 user-mode as BEPeter Crosthwaite2016-03-041-1/+16
* target-arm: cpu: Move cpu_is_big_endian to headerPeter Crosthwaite2016-03-042-16/+22
* target-arm: implement SCTLR.B, drop bswap_codePaolo Bonzini2016-03-047-29/+60
* target-arm: Correct handling of writes to CPSR mode bits from gdb in usermodePeter Maydell2016-03-041-2/+9
* tcg: Add type for vCPU pointersLluís Vilanova2016-03-012-2/+2
* target-arm: Make reserved ranges in ID_AA64* spaces RAZ, not UNDEFPeter Maydell2016-02-262-7/+122
* target-arm: Mark CNTHP_TVAL_EL2 as ARM_CP_NO_RAWEdgar E. Iglesias2016-02-261-1/+1
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