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path: root/target-mips/cpu.h
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* Merge remote-tracking branch 'remotes/lalrae/tags/mips-20150311' into stagingPeter Maydell2015-03-111-2/+17
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| * target-mips: add missing MSACSR and restore fp_status and hflagsLeon Alrae2015-03-111-0/+17
| * target-mips: replace cpu_save/cpu_load with VMStateDescriptionLeon Alrae2015-03-111-2/+0Star
* | cpu: Make cpu_init() return QOM CPUState objectEduardo Habkost2015-03-101-8/+1Star
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* exec.c: Drop TARGET_HAS_ICE define and checksPeter Maydell2015-01-201-1/+0Star
* target-mips: Add missing calls to synchronise SoftFloat statusMaciej W. Rozycki2014-12-161-0/+12
* target-mips: Correct 32-bit address space wrappingMaciej W. Rozycki2014-12-161-3/+5
* target-mips: Tighten ISA level checksMaciej W. Rozycki2014-12-161-3/+4
* target-mips: Correct the writes to Status and Cause registers via gdbstubMaciej W. Rozycki2014-12-161-0/+89
* target-mips: Make CP0.Config4 and CP0.Config5 registers signedMaciej W. Rozycki2014-12-161-4/+4
* mips: Add macros for CP0.Config3 and CP0.Config4 bitsMaciej W. Rozycki2014-11-071-0/+13
* target-mips: remove duplicated mips/ieee mapping functionYongbok Kim2014-11-031-0/+4
* target-mips: add MSA defines and data structureYongbok Kim2014-11-031-2/+50
* target-mips: CP0_Status.CU0 no longer allows the user to access CP0Leon Alrae2014-11-031-1/+2
* target-mips: implement forbidden slotLeon Alrae2014-11-031-1/+2
* target-mips: add Config5.SBRILeon Alrae2014-11-031-2/+9
* target-mips: update cpu_save/cpu_load to support new registersLeon Alrae2014-11-031-1/+1
* target-mips: add BadInstr and BadInstrP supportLeon Alrae2014-11-031-0/+6
* target-mips: add TLBINV supportLeon Alrae2014-11-031-0/+7
* target-mips: add new Read-Inhibit and Execute-Inhibit exceptionsLeon Alrae2014-11-031-1/+4
* target-mips: update PageGrain and m{t,f}c0 EntryLo{0,1}Leon Alrae2014-11-031-0/+4
* target-mips: add RI and XI fields to TLB entryLeon Alrae2014-11-031-0/+11
* target-mips: add KScratch registersLeon Alrae2014-11-031-0/+3
* target-mips: fix broken MIPS16 and microMIPSYongbok Kim2014-10-141-6/+7
* target-mips: Status.UX/SX/KX enable 32-bit address wrappingLeon Alrae2014-10-131-4/+14
* target-mips: implement UserLocal RegisterPetar Jovanovic2014-06-181-4/+7
* softmmu: move ALIGNED_ONLY to cpu.hPaolo Bonzini2014-06-051-0/+1
* target-mips: Avoid shifting left into sign bitPeter Maydell2014-03-271-1/+1
* cpu: Move breakpoints field from CPU_COMMON to CPUStateAndreas Färber2014-03-131-0/+1
* cpu: Turn cpu_handle_mmu_fault() into a CPUClass hookAndreas Färber2014-03-131-3/+2Star
* cpu: Turn cpu_has_work() into a CPUClass hookAndreas Färber2014-03-131-28/+0Star
* target-mips: add support for CP0_Config5Petar Jovanovic2014-02-101-0/+10
* target-mips: add support for CP0_Config4Petar Jovanovic2014-02-101-0/+3
* misc: Replace 'struct QEMUTimer' by 'QEMUTimer'Stefan Weil2013-12-021-1/+1
* cpu: Introduce CPUClass::synchronize_from_tb() for cpu_pc_from_tb()Andreas Färber2013-07-231-7/+0Star
* linux-user: Move cpu_clone_regs() and cpu_set_tls() into linux-userPeter Maydell2013-07-091-13/+0Star
* cpu: Turn cpu_unassigned_access() into a CPUState hookAndreas Färber2013-06-281-2/+3
* linux-user: Save the correct resume address for MIPS signal handlingKwok Cheung Yeung2013-05-201-0/+1
* cpu: Replace do_interrupt() by CPUClass::do_interrupt methodAndreas Färber2013-03-121-1/+0Star
* cpu: Move halted and interrupt_request fields to CPUStateAndreas Färber2013-03-121-2/+2
* mips-linux-user: Save and restore fpu and dsp from sigcontextRichard Henderson2013-03-051-0/+3
* target-mips: Move TCG initialization to MIPSCPU initfnAndreas Färber2013-02-161-0/+1
* target-mips: Allow DSP access to be disabled once enabled.Eric Johnson2013-01-081-1/+1
* fpu: move public header file to include/fpuPaolo Bonzini2012-12-191-1/+1
* exec: move include files to include/exec/Paolo Bonzini2012-12-191-3/+3
* Merge remote-tracking branch 'afaerber/qom-cpu' into stagingAnthony Liguori2012-11-011-5/+6
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| * cpus: Pass CPUState to [qemu_]cpu_has_work()Andreas Färber2012-10-311-5/+6
* | target-mips: Add ASE DSP resources access checkJia Liu2012-10-311-2/+21
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* Rename target_phys_addr_t to hwaddrAvi Kivity2012-10-231-6/+6
* target-mips: switch to AREG0 free modeBlue Swirl2012-09-151-8/+8
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