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path: root/target-mips/cpu.h
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* cpu: move exec-all.h inclusion out of cpu.hPaolo Bonzini2016-05-191-2/+0Star
* mips: move CP0 functions out of cpu.hPaolo Bonzini2016-05-191-109/+4Star
* qemu-common: push cpu.h inclusion out of qemu-common.hPaolo Bonzini2016-05-191-16/+2Star
* target-mips: make cpu-qom.h not target specificPaolo Bonzini2016-05-191-1/+37
* tb: consistently use uint32_t for tb->flagsEmilio G. Cota2016-05-131-1/+1
* target-mips: add MAAR, MAARI registerYongbok Kim2016-03-301-0/+4
* target-mips: make ITC Configuration Tags accessible to the CPULeon Alrae2016-03-301-1/+6
* hw/mips: implement ITC Configuration Tags and Storage CellsLeon Alrae2016-03-301-0/+1
* hw/mips_malta: add CPS to Malta boardLeon Alrae2016-03-301-0/+1
* target-mips: add CMGCRBase registerYongbok Kim2016-03-301-1/+2
* target-mips: indicate presence of IEEE 754-2008 FPU in R6/R5+MSA CPUsLeon Alrae2016-03-231-0/+3
* target-mips: implement R6 multi-threadingYongbok Kim2016-02-261-0/+25
* all: Clean up includesPeter Maydell2016-02-231-1/+0Star
* target-mips: Stop using uint_fast*_t types in r4k_tlb_t structPeter Maydell2016-02-191-13/+13
* target-mips/cpu.h: Fix spell errorDongxue Zhang2016-01-231-1/+1
* target-mips: flush QEMU TLB when disabling 64-bit addressingLeon Alrae2015-11-241-1/+17
* target-mips: add PC, XNP reg numbers to RDHWRYongbok Kim2015-10-301-0/+1
* target-mips: update writing to CP0.Status.KX/SX/UX in MIPS Release R6Leon Alrae2015-10-291-1/+6
* target-mips: move the test for enabled interrupts to a separate functionLeon Alrae2015-10-291-14/+15
* target-*: Drop cpu_gen_code defineRichard Henderson2015-10-071-1/+0Star
* target-mips: Add delayed branch state to insn_startRichard Henderson2015-10-071-0/+1
* mips: Remove ELF_MACHINE from cpu.hPeter Crosthwaite2015-09-251-2/+0Star
* target-mips: improve exception handlingPavel Dovgaluk2015-09-181-0/+24
* tlb: Add "ifetch" argument to cpu_mmu_index()Benjamin Herrenschmidt2015-09-111-1/+1
* target-mips: update mips32r5-generic into P5600Yongbok Kim2015-08-131-1/+1
* cpu-exec: Purge all uses of ENV_GET_CPU()Peter Crosthwaite2015-07-091-1/+1
* target-mips: add MTHC0 and MFHC0 instructionsLeon Alrae2015-06-121-0/+1
* target-mips: add CP0.PageGrain.ELPA supportLeon Alrae2015-06-121-2/+25
* target-mips: extend selected CP0 registers to 64-bits in MIPS32Leon Alrae2015-06-121-7/+7
* target-mips: add ERETNC instruction and Config5.LLB bitLeon Alrae2015-06-111-0/+1
* target-mips: add Config5.FRE support allowing Status.FR=0 emulationLeon Alrae2015-06-111-2/+11
* Merge remote-tracking branch 'remotes/lalrae/tags/mips-20150311' into stagingPeter Maydell2015-03-111-2/+17
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| * target-mips: add missing MSACSR and restore fp_status and hflagsLeon Alrae2015-03-111-0/+17
| * target-mips: replace cpu_save/cpu_load with VMStateDescriptionLeon Alrae2015-03-111-2/+0Star
* | cpu: Make cpu_init() return QOM CPUState objectEduardo Habkost2015-03-101-8/+1Star
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* exec.c: Drop TARGET_HAS_ICE define and checksPeter Maydell2015-01-201-1/+0Star
* target-mips: Add missing calls to synchronise SoftFloat statusMaciej W. Rozycki2014-12-161-0/+12
* target-mips: Correct 32-bit address space wrappingMaciej W. Rozycki2014-12-161-3/+5
* target-mips: Tighten ISA level checksMaciej W. Rozycki2014-12-161-3/+4
* target-mips: Correct the writes to Status and Cause registers via gdbstubMaciej W. Rozycki2014-12-161-0/+89
* target-mips: Make CP0.Config4 and CP0.Config5 registers signedMaciej W. Rozycki2014-12-161-4/+4
* mips: Add macros for CP0.Config3 and CP0.Config4 bitsMaciej W. Rozycki2014-11-071-0/+13
* target-mips: remove duplicated mips/ieee mapping functionYongbok Kim2014-11-031-0/+4
* target-mips: add MSA defines and data structureYongbok Kim2014-11-031-2/+50
* target-mips: CP0_Status.CU0 no longer allows the user to access CP0Leon Alrae2014-11-031-1/+2
* target-mips: implement forbidden slotLeon Alrae2014-11-031-1/+2
* target-mips: add Config5.SBRILeon Alrae2014-11-031-2/+9
* target-mips: update cpu_save/cpu_load to support new registersLeon Alrae2014-11-031-1/+1
* target-mips: add BadInstr and BadInstrP supportLeon Alrae2014-11-031-0/+6
* target-mips: add TLBINV supportLeon Alrae2014-11-031-0/+7
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