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path: root/target-mips/helper.h
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* target-mips: add MAAR, MAARI registerYongbok Kim2016-03-301-0/+6
* target-mips: make ITC Configuration Tags accessible to the CPULeon Alrae2016-03-301-0/+3
* target-mips: implement R6 multi-threadingYongbok Kim2016-02-261-0/+4
* target-mips: add PC, XNP reg numbers to RDHWRYongbok Kim2015-10-301-0/+2
* target-mips: improve exception handlingPavel Dovgaluk2015-09-181-0/+1
* target-mips: add Unified Hosting Interface (UHI) supportLeon Alrae2015-06-261-0/+2
* target-mips: add ERETNC instruction and Config5.LLB bitLeon Alrae2015-06-111-0/+1
* target-mips: Misaligned memory accesses for MSAYongbok Kim2015-06-111-2/+8
* target-mips: Fix CP0.Config3.ISAOnExc write accessesMaciej W. Rozycki2014-12-161-0/+1
* target-mips: add MSA MI10 format instructionsYongbok Kim2014-11-031-0/+3
* target-mips: add MSA 2RF format instructionsYongbok Kim2014-11-031-0/+17
* target-mips: add MSA VEC/2R format instructionsYongbok Kim2014-11-031-0/+12
* target-mips: add MSA 3RF format instructionsYongbok Kim2014-11-031-0/+42
* target-mips: add MSA ELM format instructionsYongbok Kim2014-11-031-0/+10
* target-mips: add MSA 3R format instructionsYongbok Kim2014-11-031-0/+64
* target-mips: add MSA BIT format instructionsYongbok Kim2014-11-031-0/+13
* target-mips: add MSA I5 format instructionYongbok Kim2014-11-031-0/+13
* target-mips: add MSA I8 format instructionsYongbok Kim2014-11-031-0/+10
* target-mips: add TLBINV supportLeon Alrae2014-11-031-0/+2
* target-mips: update PageGrain and m{t,f}c0 EntryLo{0,1}Leon Alrae2014-11-031-0/+5
* target-mips: add new Floating Point Comparison instructionsYongbok Kim2014-10-141-0/+27
* target-mips: add new Floating Point instructionsLeon Alrae2014-10-141-0/+20
* target-mips: add ALIGN, DALIGN, BITSWAP and DBITSWAP instructionsYongbok Kim2014-10-131-0/+5
* tcg: Invert the inclusion of helper.hRichard Henderson2014-05-281-6/+0Star
* target-mips: add user-mode FR switch support for MIPS32r5Petar Jovanovic2014-02-101-1/+1
* target-mips: add support for CP0_Config5Petar Jovanovic2014-02-101-0/+1
* target-mips: add support for CP0_Config4Petar Jovanovic2014-02-101-0/+1
* tcg: Remove stray semi-colons from target-*/helper.hRichard Henderson2013-10-101-6/+6
* target-mips: Use mul[us]2 in [D]MULT[U] insnsRichard Henderson2013-02-231-2/+0Star
* target-mips: implement DSP (d)append sub-class with TCGAurelien Jarno2013-01-311-13/+0Star
* exec: move include files to include/exec/Paolo Bonzini2012-12-191-2/+2
* target-mips: implement unaligned loads using TCGAurelien Jarno2012-10-311-4/+0Star
* target-mips: use the softfloat floatXX_muladd functionsAurelien Jarno2012-10-311-4/+4
* target-mips: Add ASE DSP accumulator instructionsJia Liu2012-10-311-0/+35
* target-mips: Add ASE DSP compare-pick instructionsJia Liu2012-10-311-0/+52
* target-mips: Add ASE DSP bit/manipulation instructionsJia Liu2012-10-311-0/+7
* target-mips: Add ASE DSP multiply instructionsJia Liu2012-10-311-0/+91
* target-mips: Add ASE DSP GPR-based shift instructionsJia Liu2012-10-311-0/+38
* target-mips: Add ASE DSP arithmetic instructionsJia Liu2012-10-311-0/+126
* target-mips: rename helper flagsAurelien Jarno2012-10-281-53/+53
* target-mips: Implement Loongson Multimedia InstructionsRichard Henderson2012-09-191-0/+59
* target-mips: switch to AREG0 free modeBlue Swirl2012-09-151-202/+208
* target-mips: Add compiler attribute to some functions which don't returnStefan Weil2012-03-241-2/+2
* mips: Hook in more reg accesses via mttr/mftrEdgar E. Iglesias2011-09-061-0/+10
* target-mips: fix translation of MT instructionsNathan Froyd2010-12-221-4/+4
* mips: more fixes to the MIPS interrupt glue logicAurelien Jarno2010-07-251-1/+0Star
* target-mips: microMIPS ASE supportNathan Froyd2010-06-091-0/+9
* target-mips: use physical address in lladdrAurelien Jarno2009-11-301-0/+9
* target-mips: make CP0_LLAddr register CPU dependentAurelien Jarno2009-11-221-0/+1
* target-mips: use the TCG_CALL_PURE and TCG_CALL_CONST for some helpersaurel322009-04-061-4/+4
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