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path: root/target-mips/op_helper.c
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* tcg: Merge GETPC and GETRARichard Henderson2016-09-161-9/+9
* Fix confusing argument names in some common functionsSergey Sorokin2016-07-121-5/+5
* target-mips: change ASID type to hold more than 8 bitsPaul Burton2016-07-121-4/+4
* target-mips: add ASID mask field and replace magic valuesPaul Burton2016-07-121-12/+15
* target-mips: Implement FCR31's R/W bitmask and related functionalitiesAleksandar Markovic2016-06-241-11/+3Star
* target-mips: Add nan2008 flavor of <CEIL|CVT|FLOOR|ROUND|TRUNC>.<L|W>.<S|D>Aleksandar Markovic2016-06-241-20/+349
* softfloat: Implement run-time-configurable meaning of signaling NaN bitAleksandar Markovic2016-06-241-5/+12
* coccinelle: Remove unnecessary variables for function return valueEduardo Habkost2016-06-201-3/+1Star
* cpu: move exec-all.h inclusion out of cpu.hPaolo Bonzini2016-05-191-0/+1
* Fix some typos found by codespellStefan Weil2016-05-181-1/+1
* target-mips: Fix RDHWR exception host PCJames Hogan2016-04-281-8/+8
* target-mips: add MAAR, MAARI registerYongbok Kim2016-03-301-0/+45
* target-mips: make ITC Configuration Tags accessible to the CPULeon Alrae2016-03-301-1/+39
* target-mips: implement R6 multi-threadingYongbok Kim2016-02-261-0/+48
* mips: Clean up includesPeter Maydell2016-01-231-1/+1
* target-mips: silence NaNs for cvt.s.d and cvt.d.sAurelien Jarno2016-01-231-0/+2
* target-mips: flush QEMU TLB when disabling 64-bit addressingLeon Alrae2015-11-241-13/+0Star
* target-mips: add PC, XNP reg numbers to RDHWRYongbok Kim2015-10-301-29/+35
* target-mips: improve exception handlingPavel Dovgaluk2015-09-181-113/+141
* target-mips: Fix RDHWR on CP0.CountAlex Smith2015-09-181-2/+7
* tlb: Add "ifetch" argument to cpu_mmu_index()Benjamin Herrenschmidt2015-09-111-2/+2
* target-mips: Use CPU_LOG_INT for logging related to interruptsRichard Henderson2015-08-131-1/+2
* target-mips: fix offset calculation for InterruptsYongbok Kim2015-07-281-2/+0Star
* target-mips: correct DERET instructionLeon Alrae2015-07-151-2/+1Star
* target-mips: fix ASID synchronisation for MIPS MTAurelien Jarno2015-07-151-1/+1
* target-mips: add CP0.PageGrain.ELPA supportLeon Alrae2015-06-121-7/+12
* target-mips: support Page Frame Number Extension fieldLeon Alrae2015-06-121-6/+26
* target-mips: extend selected CP0 registers to 64-bits in MIPS32Leon Alrae2015-06-121-4/+4
* target-mips: add ERETNC instruction and Config5.LLB bitLeon Alrae2015-06-111-1/+11
* target-mips: Misaligned memory accesses for MSAYongbok Kim2015-06-111-66/+77
* target-mips: add Config5.FRE support allowing Status.FR=0 emulationLeon Alrae2015-06-111-0/+34
* target-mips: ll and lld cause AdEL exception for unaligned addressLeon Alrae2015-02-131-3/+7
* target-mips: Don't use _raw load/store accessorsPeter Maydell2015-01-201-2/+2
* target-mips: Add missing calls to synchronise SoftFloat statusMaciej W. Rozycki2014-12-161-12/+0Star
* target-mips: Also apply the CP0.Status mask to MTTC0Maciej W. Rozycki2014-12-161-1/+2
* target-mips: Fix CP0.Config3.ISAOnExc write accessesMaciej W. Rozycki2014-12-161-0/+8
* target-mips: Correct the writes to Status and Cause registers via gdbstubMaciej W. Rozycki2014-12-161-84/+7Star
* target-mips: Correct the handling of writes to CP0.Status for MIPSr6Maciej W. Rozycki2014-12-161-2/+4
* target-mips: Restore the order of helpersMaciej W. Rozycki2014-12-161-159/+160
* target-mips: Remove unused `FLOAT_OP' macroMaciej W. Rozycki2014-12-161-2/+0Star
* target-mips: Make `helper_float_cvtw_s' consistent with the remaining helpersMaciej W. Rozycki2014-12-161-1/+1
* target-mips: add MSA MI10 format instructionsYongbok Kim2014-11-031-4/+80
* target-mips: remove duplicated mips/ieee mapping functionYongbok Kim2014-11-031-2/+2
* target-mips: add MSA defines and data structureYongbok Kim2014-11-031-0/+1
* target-mips: add restrictions for possible values in registersLeon Alrae2014-11-031-17/+53
* target-mips: add BadInstr and BadInstrP supportLeon Alrae2014-11-031-2/+15
* target-mips: add TLBINV supportLeon Alrae2014-11-031-7/+58
* target-mips: update PageGrain and m{t,f}c0 EntryLo{0,1}Leon Alrae2014-11-031-3/+22
* target-mips: add RI and XI fields to TLB entryLeon Alrae2014-11-031-0/+8
* target-mips: add ULL suffix in bitswap to avoid compiler warningLeon Alrae2014-10-241-6/+6
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