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path: root/target-mips/translate.c
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* cpu: move exec-all.h inclusion out of cpu.hPaolo Bonzini2016-05-191-0/+1
* tcg: Allow goto_tb to any target PC in user modeSergey Fedorov2016-05-131-5/+15
* target-mips: add MAAR, MAARI registerYongbok Kim2016-03-301-0/+52
* target-mips: use CP0_CHECK for gen_m{f|t}hc0Yongbok Kim2016-03-301-25/+21Star
* target-mips: make ITC Configuration Tags accessible to the CPULeon Alrae2016-03-301-10/+52
* target-mips: check CP0 enabled for CACHE instruction also in R6Leon Alrae2016-03-301-0/+1
* hw/mips_malta: add CPS to Malta boardLeon Alrae2016-03-301-0/+10
* target-mips: add CMGCRBase registerYongbok Kim2016-03-301-0/+18
* target-mips: indicate presence of IEEE 754-2008 FPU in R6/R5+MSA CPUsLeon Alrae2016-03-231-0/+1
* tcg: Add type for vCPU pointersLluís Vilanova2016-03-011-1/+1
* target-mips: implement R6 multi-threadingYongbok Kim2016-02-261-0/+59
* tcg: Change tcg_global_mem_new_* to take a TCGv_ptrRichard Henderson2016-02-091-12/+13
* log: do not unnecessarily include qom/cpu.hPaolo Bonzini2016-02-031-0/+1
* mips: Clean up includesPeter Maydell2016-01-231-0/+1
* target-mips: Fix ALIGN instruction when bp=0Miodrag Dinic2016-01-231-1/+10
* target-mips: add SIGRIE instructionYongbok Kim2015-10-301-1/+11
* target-mips: add PC, XNP reg numbers to RDHWRYongbok Kim2015-10-301-3/+25
* target-mips: Add enum for BREAK32Yongbok Kim2015-10-291-1/+2
* target-*: Advance pc after recognizing a breakpointRichard Henderson2015-10-281-2/+4
* tcg: Remove gen_intermediate_code_pcRichard Henderson2015-10-071-43/+5Star
* tcg: Pass data argument to restore_state_to_opcRichard Henderson2015-10-071-4/+5
* tcg: Add TCG_MAX_INSNSRichard Henderson2015-10-071-1/+6
* target-mips: Add delayed branch state to insn_startRichard Henderson2015-10-071-1/+2
* target-*: Introduce and use cpu_breakpoint_testRichard Henderson2015-10-071-15/+10Star
* target-*: Increment num_insns immediately after tcg_gen_insn_startRichard Henderson2015-10-071-3/+2Star
* target-*: Unconditionally emit tcg_gen_insn_startRichard Henderson2015-10-071-5/+4Star
* tcg: Rename debug_insn_start to insn_startRichard Henderson2015-10-071-1/+1
* target-mips: improve exception handlingPavel Dovgaluk2015-09-181-191/+174Star
* target-mips: correct MTC0 instruction on MIPS64Leon Alrae2015-09-181-11/+7Star
* target-mips: add missing restriction in DAUI instructionLeon Alrae2015-09-181-1/+3
* target-mips: get rid of MIPS_DEBUG_SIGN_EXTENSIONSAurelien Jarno2015-09-181-39/+0Star
* target-mips: get rid of MIPS_DEBUGAurelien Jarno2015-09-181-605/+19Star
* target-mips: remove wrong checks for recip.fmt and rsqrt.fmtPetar Jovanovic2015-09-181-4/+2Star
* target-mips: Use tcg_gen_extrh_i64_i32Richard Henderson2015-09-181-26/+22Star
* tcg: Remove tcg_gen_trunc_i64_i32Richard Henderson2015-08-241-2/+2
* target-mips: simplify LWL/LDL mask generationAurelien Jarno2015-08-131-8/+6Star
* target-mips: Copy restrictions from ext/ins to dext/dinsRichard Henderson2015-08-041-20/+25
* target-mips: fix semihosting for microMIPS R6Leon Alrae2015-08-041-3/+7
* target-mips: fix page fault address for LWL/LWR/LDL/LDRAurelien Jarno2015-07-151-0/+12
* target-mips: fix logically dead code reported by CoverityLeon Alrae2015-07-151-0/+3
* target-mips: microMIPS32 R6 POOL16{A, C} instructionsYongbok Kim2015-06-261-15/+118
* target-mips: microMIPS32 R6 Major instructionsYongbok Kim2015-06-261-17/+45
* target-mips: microMIPS32 R6 POOL32{I, C} instructionsYongbok Kim2015-06-261-6/+21
* target-mips: microMIPS32 R6 POOL32F instructionsYongbok Kim2015-06-261-32/+199
* target-mips: microMIPS32 R6 POOL32A{XF} instructionsYongbok Kim2015-06-261-10/+72
* target-mips: microMIPS32 R6 branches and jumpsYongbok Kim2015-06-261-40/+202
* target-mips: add microMIPS32 R6 opcode enumYongbok Kim2015-06-261-16/+103
* target-mips: signal RI for removed instructions in microMIPS R6Yongbok Kim2015-06-261-0/+68
* target-mips: raise RI exceptions when FIR.PS = 0Yongbok Kim2015-06-261-33/+45
* target-mips: rearrange gen_compute_compact_branchYongbok Kim2015-06-261-236/+236
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