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path: root/target-ppc/translate_init.c
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* ppc: POWER7 has lq/stq instructions and stq need to check ISABenjamin Herrenschmidt2016-06-071-1/+1
* ppc: POWER7 had ACOP and PID registersBenjamin Herrenschmidt2016-06-071-0/+18
* ppc: Better figure out if processor has HV modeBenjamin Herrenschmidt2016-06-071-4/+15
* ppc: Add PPC_64H instruction flag to POWER7 and POWER8Benjamin Herrenschmidt2016-05-301-2/+2
* PPC/KVM: early validation of vcpu idGreg Kurz2016-05-271-0/+8
* ppc: use PowerPCCPU instead of CPUPPCStatePaolo Bonzini2016-05-191-54/+38Star
* ppc: Rework POWER7 & POWER8 exception modelCédric Le Goater2016-04-051-1/+1
* ppc: move POWER8 Book4 regs in their own routineCédric Le Goater2016-03-241-0/+8
* ppc: A couple more dummy POWER8 Book4 regsBenjamin Herrenschmidt2016-03-241-0/+12
* ppc: Add dummy CIABR SPRBenjamin Herrenschmidt2016-03-241-0/+5
* ppc: Add POWER8 IAMR registerBenjamin Herrenschmidt2016-03-241-2/+39
* ppc: Fix writing to AMR/UAMORBenjamin Herrenschmidt2016-03-241-15/+59
* ppc: Initialize AMOR in PAPR modeBenjamin Herrenschmidt2016-03-241-0/+4
* ppc: Add dummy SPR_IC for POWER8Benjamin Herrenschmidt2016-03-241-0/+12
* ppc: Create cpu_ppc_set_papr() helperBenjamin Herrenschmidt2016-03-241-1/+22
* ppc: Add a bunch of hypervisor SPRs to Book3sBenjamin Herrenschmidt2016-03-241-0/+21
* ppc: Add macros to register hypervisor mode SPRsBenjamin Herrenschmidt2016-03-241-4/+31
* ppc64: set MSR_SF bitLaurent Vivier2016-03-241-1/+1
* target-ppc: Add PVR for POWER8NVL processorAlexey Kardashevskiy2016-03-151-0/+3
* ppc: Add a few more P8 PMU SPRsBenjamin Herrenschmidt2016-03-151-0/+28
* ppc: Fix migration of the TAR SPRThomas Huth2016-03-151-4/+4
* ppc: Define the PSPB register on POWER8Thomas Huth2016-03-151-0/+9
* qom: Swap 'name' next to visitor in ObjectPropertyAccessorEric Blake2016-02-081-4/+4
* qapi: Swap visit_* arguments for consistent 'name' placementEric Blake2016-02-081-2/+2
* target-ppc: Allow more page sizes for POWER7 & POWER8 in TCGDavid Gibson2016-01-301-0/+32
* target-ppc: gdbstub: Add VSX supportAnton Blanchard2016-01-301-0/+24
* target-ppc: gdbstub: fix spe registers for little-endian guestsGreg Kurz2016-01-301-1/+10
* target-ppc: gdbstub: fix altivec registers for little-endian guestsGreg Kurz2016-01-301-2/+10
* target-ppc: gdbstub: introduce avr_need_swap()Greg Kurz2016-01-301-14/+23
* target-ppc: gdbstub: fix float registers for little-endian guestsGreg Kurz2016-01-301-0/+4
* ppc: Clean up error handling in ppc_set_compat()David Gibson2016-01-301-6/+7
* ppc: Clean up includesPeter Maydell2016-01-291-3/+1Star
* gdb: provide the name of the architecture in the target.xmlDavid Hildenbrand2016-01-271-0/+10
* dump: qemunotes aren't commonly neededAndrew Jones2016-01-151-1/+0Star
* taget-ppc: Fix read access to IBAT registers higher than IBAT3Julio Guerra2015-11-061-1/+1
* ppc/spapr: Add "ibm,pa-features" property to the device-treeBenjamin Herrenschmidt2015-10-231-0/+1
* ppc: Add mmu_model defines for arch 2.03 and 2.07Benjamin Herrenschmidt2015-10-231-2/+2
* Target-ppc: Remove unnecessary variableShraddha Barke2015-09-111-7/+2Star
* cpu: Change cpu_exec_init() arg to cpu, not envPeter Crosthwaite2015-07-091-1/+1
* target-ppc: Move cpu_exec_init() call to realize functionBharata B Rao2015-07-091-2/+10
* cpu: Add Error argument to cpu_exec_init()Bharata B Rao2015-07-091-1/+1
* PPC: Introduce the Virtual Time Base (VTB) SPR registerCyril Bur2015-03-091-0/+10
* Merge remote-tracking branch 'remotes/agraf/tags/signed-ppc-for-upstream' int...Peter Maydell2015-01-101-2/+3
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| * target-ppc: Power8 Supports Transactional MemoryTom Musta2015-01-071-2/+3
* | translate: check cflags instead of use_icount globalPaolo Bonzini2015-01-031-12/+12
* | target-ppc: pass DisasContext to SPR generator functionsPaolo Bonzini2014-12-231-126/+121Star
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* target-ppc: Fix breakpoint registers for e300Fabien Chouteau2014-11-201-26/+26
* target-ppc: Fix an invalid free in opcode table handling code.Bharata B Rao2014-11-041-3/+16
* target-ppc: Use macros in opcodes table handling codeBharata B Rao2014-11-041-10/+14
* target-ppc : Add new processor type 440x5wDFPUPierre Mallard2014-11-041-0/+38
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