| Commit message (Expand) | Author | Age | Files | Lines |
|---|
| * | target-ppc: add vmul10[u,eu,cu,ecu]q instructions | Vasant Hegde | 2016-10-28 | 2 | -4/+76 |
| * | ppc: Fix single step with gdb stub | Benjamin Herrenschmidt | 2016-10-28 | 1 | -1/+1 |
| * | ppc: fix MSR_ME handling for system reset interrupt | Nicholas Piggin | 2016-10-28 | 1 | -2/+2 |
| * | target-ppc: implement xxbr[qdwh] instruction | Nikunj A Dadhania | 2016-10-28 | 3 | -0/+117 |
| * | target-ppc: implement vnegw/d instructions | Nikunj A Dadhania | 2016-10-28 | 4 | -0/+18 |
| * | exec: call cpu_exec_exit() from a CPU unrealize common function | Laurent Vivier | 2016-10-24 | 2 | -1/+9 |
| * | exec: move cpu_exec_init() calls to realize functions | Laurent Vivier | 2016-10-24 | 1 | -1/+1 |
| * | target-ppc: implement vexts[bh]2w and vexts[bhw]2d | Nikunj A Dadhania | 2016-10-14 | 4 | -0/+30 |
| * | target-ppc: fix vmx instruction type/type2 | Nikunj A Dadhania | 2016-10-05 | 2 | -24/+24 |
| * | target-ppc/kvm: Enable transactional memory on POWER8 with KVM-HV, too | Thomas Huth | 2016-10-05 | 1 | -1/+8 |
| * | target-ppc/kvm: Add a wrapper function to check for KVM-PR | Thomas Huth | 2016-10-05 | 1 | -10/+16 |
| * | target-ppc: Implement mtvsrws instruction | Ravi Bangoria | 2016-10-05 | 2 | -0/+20 |
| * | target-ppc: add vclzlsbb/vctzlsbb instructions | Rajalakshmi Srinivasaraghavan | 2016-10-05 | 4 | -0/+48 |
| * | target-ppc: add vector compare not equal instructions | Rajalakshmi Srinivasaraghavan | 2016-10-05 | 4 | -16/+38 |
| * | target-ppc: fix invalid mask - cmpl, bctar | Avinesh Kumar | 2016-10-05 | 1 | -2/+2 |
| * | target-ppc: add stxvb16x instruction | Nikunj A Dadhania | 2016-10-05 | 2 | -0/+20 |
| * | target-ppc: add lxvb16x instruction | Nikunj A Dadhania | 2016-10-05 | 2 | -0/+20 |
| * | target-ppc: add stxvh8x instruction | Nikunj A Dadhania | 2016-10-05 | 2 | -0/+32 |
| * | target-ppc: add lxvh8x instruction | Nikunj A Dadhania | 2016-10-05 | 2 | -0/+50 |
| * | target-ppc: improve stxvw4x implementation | Nikunj A Dadhania | 2016-10-05 | 1 | -14/+19 |
| * | target-ppc: improve lxvw4x implementation | Nikunj A Dadhania | 2016-10-05 | 1 | -14/+18 |
| * | target-ppc: Implement mtvsrdd instruction | Ravi Bangoria | 2016-10-05 | 2 | -0/+24 |
| * | target-ppc: Implement mfvsrld instruction | Ravi Bangoria | 2016-10-05 | 2 | -0/+18 |
| * | ppc: Check the availability of transactional memory | Thomas Huth | 2016-10-05 | 2 | -0/+13 |
| * | linux-user: remove #define smp_{cores, threads} | Marc-André Lureau | 2016-09-27 | 1 | -1/+2 |
| * | ppc/kvm: Mark 64kB page size support as disabled if not available | Thomas Huth | 2016-09-23 | 1 | -0/+7 |
| * | Enable H_CLEAR_MOD and H_CLEAR_REF hypercalls on KVM/PPC64. | Nathan Whitehorn | 2016-09-23 | 2 | -0/+11 |
| * | target-ppc: tlbie/tlbivax should have global effect | Nikunj A Dadhania | 2016-09-23 | 5 | -4/+32 |
| * | target-ppc: add flag in check_tlb_flush() | Nikunj A Dadhania | 2016-09-23 | 5 | -17/+26 |
| * | target-ppc: add TLB_NEED_LOCAL_FLUSH flag | Nikunj A Dadhania | 2016-09-23 | 4 | -7/+8 |
| * | spapr: Introduce sPAPRCPUCoreClass | Bharata B Rao | 2016-09-23 | 1 | -16/+6 |
| * | target-ppc: implement darn instruction | Ravi Bangoria | 2016-09-23 | 3 | -0/+38 |
| * | target-ppc: add stxsi[bh]x instruction | Nikunj A Dadhania | 2016-09-23 | 3 | -0/+7 |
| * | target-ppc: add lxsi[bw]zx instruction | Nikunj A Dadhania | 2016-09-23 | 3 | -0/+6 |
| * | target-ppc: add xxspltib instruction | Nikunj A Dadhania | 2016-09-23 | 3 | -0/+27 |
| * | target-ppc: consolidate store conditional | Nikunj A Dadhania | 2016-09-23 | 1 | -34/+24 |
| * | target-ppc: move out stqcx impementation | Nikunj A Dadhania | 2016-09-23 | 1 | -22/+47 |
| * | target-ppc: consolidate load with reservation | Nikunj A Dadhania | 2016-09-23 | 1 | -11/+11 |
| * | target-ppc: convert st[16,32,64]r to use new macro | Nikunj A Dadhania | 2016-09-23 | 1 | -22/+10 |
| * | target-ppc: convert st64 to use new macro | Nikunj A Dadhania | 2016-09-23 | 6 | -53/+48 |
| * | target-ppc: consolidate store operations | Nikunj A Dadhania | 2016-09-23 | 1 | -19/+16 |
| * | target-ppc: convert ld[16,32,64]ur to use new macro | Nikunj A Dadhania | 2016-09-23 | 1 | -17/+10 |
| * | target-ppc: convert ld64 to use new macro | Nikunj A Dadhania | 2016-09-23 | 5 | -54/+49 |
| * | target-ppc: consolidate load operations | Nikunj A Dadhania | 2016-09-23 | 1 | -38/+20 |
| * | target-ppc: add vector permute right indexed instruction | Rajalakshmi Srinivasaraghavan | 2016-09-23 | 4 | -0/+43 |
| * | target-ppc: add vector bit permute doubleword instruction | Rajalakshmi Srinivasaraghavan | 2016-09-23 | 4 | -0/+23 |
| * | target-ppc: add vector count trailing zeros instructions | Rajalakshmi Srinivasaraghavan | 2016-09-23 | 4 | -0/+46 |
| * | target-ppc: add vector extract instructions | Rajalakshmi Srinivasaraghavan | 2016-09-23 | 4 | -3/+46 |
| * | target-ppc: add vector insert instructions | Rajalakshmi Srinivasaraghavan | 2016-09-23 | 5 | -5/+71 |
| * | ppc: restrict the use of the rfi instruction | Benjamin Herrenschmidt | 2016-09-23 | 1 | -3/+6 |
