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* Move target-* CPU file into a target/ folderThomas Huth2016-12-201-168/+0Star
| | | | | | | | | | | | | | | | | | | | | | | | | We've currently got 18 architectures in QEMU, and thus 18 target-xxx folders in the root folder of the QEMU source tree. More architectures (e.g. RISC-V, AVR) are likely to be included soon, too, so the main folder of the QEMU sources slowly gets quite overcrowded with the target-xxx folders. To disburden the main folder a little bit, let's move the target-xxx folders into a dedicated target/ folder, so that target-xxx/ simply becomes target/xxx/ instead. Acked-by: Laurent Vivier <laurent@vivier.eu> [m68k part] Acked-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> [tricore part] Acked-by: Michael Walle <michael@walle.cc> [lm32 part] Acked-by: Cornelia Huck <cornelia.huck@de.ibm.com> [s390x part] Reviewed-by: Christian Borntraeger <borntraeger@de.ibm.com> [s390x part] Acked-by: Eduardo Habkost <ehabkost@redhat.com> [i386 part] Acked-by: Artyom Tarasenko <atar4qemu@gmail.com> [sparc part] Acked-by: Richard Henderson <rth@twiddle.net> [alpha part] Acked-by: Max Filippov <jcmvbkbc@gmail.com> [xtensa part] Reviewed-by: David Gibson <david@gibson.dropbear.id.au> [ppc part] Acked-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> [cris&microblaze part] Acked-by: Guan Xuetao <gxt@mprc.pku.edu.cn> [unicore32 part] Signed-off-by: Thomas Huth <thuth@redhat.com>
* target-sparc: Implement ldqf and stqf inlineRichard Henderson2016-10-311-2/+0Star
| | | | | | | | At the same time, fix a problem with stqf_asi, when a write might access two pages. Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Signed-off-by: Richard Henderson <rth@twiddle.net>
* target-sparc: Remove asi helper code handled inlineRichard Henderson2016-10-311-1/+0Star
| | | | | | | | | Now that we never call out to helpers when direct accesses can handle an asi, remove the corresponding code in those helpers. For ldda, this removes the entire helper. Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Signed-off-by: Richard Henderson <rth@twiddle.net>
* target-sparc: Implement cas_asi/casx_asi inlineRichard Henderson2016-10-311-4/+0Star
| | | | | Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Signed-off-by: Richard Henderson <rth@twiddle.net>
* target-sparc: Use explicit writes to cpu_fsrRichard Henderson2016-07-121-55/+57
| | | | | | | | | | By arranging for explicit writes to cpu_fsr after floating point operations, we are able to mark the helpers as not writing to tcg globals, which means that we don't need to invalidate the integer register set across said calls. Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Signed-off-by: Richard Henderson <rth@twiddle.net>
* target-sparc: Remove helper_ldf_asi, helper_stf_asiRichard Henderson2016-07-121-2/+0Star
| | | | | | | | We've now implemented all fp asis inline, except for the no-fault memory reads. The latter can be passed directly to helper_ld_asi. Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Signed-off-by: Richard Henderson <rth@twiddle.net>
* target-sparc: Pass TCGMemOp constants to helper_ld/st_asiRichard Henderson2016-07-121-2/+2
| | | | | | | | Reduces the argument count for helper_ld_asi; do helper_st_asi for consistency. Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Signed-off-by: Richard Henderson <rth@twiddle.net>
* target-sparc: Use QT0 to return results from lddaRichard Henderson2016-07-121-1/+1
| | | | | | | Also implement a few more twinx asis. Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Signed-off-by: Richard Henderson <rth@twiddle.net>
* target-sparc: Remove softint as a TCG globalRichard Henderson2016-07-121-3/+3
| | | | | | | | | | The global is only ever read for one insn; we can just as well use a load from env instead and generate the same code. This also allows us to indicate the the associated helpers do not touch TCG globals. Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Signed-off-by: Richard Henderson <rth@twiddle.net>
* target-sparc: Mark more flags for helpersRichard Henderson2016-07-121-24/+24
| | | | | | | Quite a few helpers do not modify tcg globals but did not so indicate. Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Signed-off-by: Richard Henderson <rth@twiddle.net>
* target-sparc: implement NPT timer bitMark Cave-Ayland2016-01-071-1/+1
| | | | | | | | | If the NPT bit is set in the timer register, all non-supervisor read accesses to the register should fail with a privilege exception. Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Reviewed-By: Artyom Tarasenko <atar4qemu@gmail.com> Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
* tcg: Invert the inclusion of helper.hRichard Henderson2014-05-281-4/+0Star
| | | | | | | | | | Rather than include helper.h with N values of GEN_HELPER, include a secondary file that sets up the macros to include helper.h. This minimizes the files that must be rebuilt when changing the macros for file N. Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <rth@twiddle.net>
* target-sparc: Add and use CPU_FEATURE_CASASebastian Huber2014-03-121-1/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The LEON3 processor has support for the CASA instruction which is normally only available for SPARC V9 processors. Binutils 2.24 and GCC 4.9 will support this instruction for LEON3. GCC uses it to generate C11 atomic operations. The CAS synthetic instruction uses an ASI of 0x80. If TARGET_SPARC64 is not defined use a supervisor data load/store for an ASI of 0x80 in helper_ld_asi()/helper_st_asi(). The supervisor data load/store was choosen according to the LEON3 documentation. The ASI 0x80 is defined in the SPARC V9 manual, Table 12—Address Space Identifiers (ASIs). Here we have: 0x80, ASI_PRIMARY, Unrestricted access, Primary address space. Tested with the following program: #include <assert.h> #include <stdatomic.h> void test(void) { atomic_int a; int e; _Bool b; atomic_store(&a, 1); e = 1; b = atomic_compare_exchange_strong(&a, &e, 2); assert(b); assert(atomic_load(&a) == 2); atomic_store(&a, 3); e = 4; b = atomic_compare_exchange_strong(&a, &e, 5); assert(!b); assert(atomic_load(&a) == 3); } Tested also on a NGMP board with a LEON4 processor. Reviewed-by: Fabien Chouteau <chouteau@adacore.com> Reviewed-by: Andreas Färber <afaerber@suse.de> Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Sebastian Huber <sebastian.huber@embedded-brains.de> Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
* tcg: Remove stray semi-colons from target-*/helper.hRichard Henderson2013-10-101-9/+9
| | | | | | | | | | | | | | | During GEN_HELPER=1, these are actually stray top-level semi-colons which are technically invalid ISO C, but GCC accepts as an extension. If we added enough __extension__ markers that we could dare use -Wpedantic, we'd see warning: ISO C does not allow extra ‘;’ outside of a function This will become a hard error in the next patch, wherein those ; will appear in the middle of a data structure. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <rth@twiddle.net>
* SPARC LEON power-down support addedRonald Hecht2013-02-231-0/+1
| | | | | | Signed-off-by: Ronald Hecht <address@hidden> Signed-off-by: Fabien Chouteau <chouteau@adacore.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
* exec: move include files to include/exec/Paolo Bonzini2012-12-191-2/+2
| | | | Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
* target-sparc: rename helper flagsAurelien Jarno2012-10-281-25/+25
| | | | | | | | | Rename helper flags to the new ones. This is purely a mechanical change, it's possible to use better flags by looking at the helpers. Acked-by: Blue Swirl <blauwirbel@gmail.com> Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* target-sparc: Move taddcctv and tsubcctv out of lineRichard Henderson2012-10-071-0/+2
| | | | | | | | | | The branches around the exception are maintaining an otherwise unnecessary use of local temps for the cpu destination. Note that gen_op_t{add,sub}_cc were identical to gen_op_{add,sub}_cc. Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
* target-sparc: Move sdivx and udivx out of lineRichard Henderson2012-10-071-0/+4
| | | | | | | | The branches around the exception are maintaining an otherwise unnecessary use of local temps for the cpu destination. Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
* target-sparc: Add compiler attribute to some functions which don't returnStefan Weil2012-03-241-1/+1
| | | | | | | | helper_raise_exception does not return, nor does do_unaligned_access. Cc: Blue Swirl <blauwirbel@gmail.com> Signed-off-by: Stefan Weil <sw@weilnetz.de> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
* Sparc: avoid AREG0 for memory access helpersBlue Swirl2012-03-181-10/+10
| | | | | | | Make memory access helpers take a parameter for CPUState instead of relying on global env. Introduce wrappers for load and store ops. Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
* Improve "ta 0" shutdownFabien Chouteau2011-11-191-1/+0Star
| | | | | | | | This patch replace the previous implementation with this simplified and more complete version (no shutdown when psret == 1). Signed-off-by: Fabien Chouteau <chouteau@adacore.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
* target-sparc: Implement FALIGNDATA inline.Richard Henderson2011-10-261-1/+0Star
| | | | | | This is a relatively simple sequence of shifts. Signed-off-by: Richard Henderson <rth@twiddle.net>
* target-sparc: Implement BMASK/BSHUFFLE.Richard Henderson2011-10-261-0/+1
| | | | Signed-off-by: Richard Henderson <rth@twiddle.net>
* target-sparc: Implement ALIGNADDR* inline.Richard Henderson2011-10-261-1/+0Star
| | | | | | | | While ALIGNADDR was implemented out-of-line, ALIGNADDRL was not implemeneted at all. However, this is a very simple operation so we're better off doing this inline. Signed-off-by: Richard Henderson <rth@twiddle.net>
* target-sparc: Implement fpack{16,32,fix}.Richard Henderson2011-10-261-0/+3
| | | | Signed-off-by: Richard Henderson <rth@twiddle.net>
* target-sparc: Implement PDIST.Richard Henderson2011-10-261-0/+1
| | | | Signed-off-by: Richard Henderson <rth@twiddle.net>
* target-sparc: Do exceptions management fully inside the helpers.Richard Henderson2011-10-261-2/+0Star
| | | | | | | | This reduces the size of the individual translation blocks, since we only emit a single call for each FOP rather than three. In addition, clear_float_exceptions expands inline to a single byte store. Signed-off-by: Richard Henderson <rth@twiddle.net>
* target-sparc: Make FPU/VIS helpers const when possible.Richard Henderson2011-10-261-22/+28
| | | | | | This also removes the unused ENV parameter from these helpers. Signed-off-by: Richard Henderson <rth@twiddle.net>
* target-sparc: Pass float64 parameters instead of dt0/1 temporaries.Richard Henderson2011-10-261-48/+47Star
| | | | Signed-off-by: Richard Henderson <rth@twiddle.net>
* Sparc: avoid AREG0 for division op helpersBlue Swirl2011-10-261-4/+4
| | | | | | | | Make [su]div{,cc} helpers take a parameter for CPUState instead of relying on global env. Move the functions to helper.c. Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
* Sparc: avoid AREG0 for softint op helpers and Leon cache controlBlue Swirl2011-10-261-3/+3
| | | | | | | | | Make softint op helpers and Leon cache irq manager take a parameter for CPUState instead of relying on global env. Move the functions to int{32,64}_helper.c. Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
* Sparc: avoid AREG0 for CWP and PSTATE helpersBlue Swirl2011-10-261-16/+16
| | | | | | | | Make CWP and PSTATE helpers take a parameter for CPUState instead of relying on global env. Remove wrapper functions. Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
* Sparc: avoid AREG0 for lazy condition code helpersBlue Swirl2011-10-231-2/+2
| | | | | | | | Make lazy condition code helpers take a parameter for CPUState instead of relying on global env. Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
* Sparc: avoid AREG0 for float and VIS opsBlue Swirl2011-10-231-86/+86
| | | | | | | | Make floating point and VIS ops take a parameter for CPUState instead of relying on global env. Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
* Sparc: avoid AREG0 for raise_exception and helper_debugBlue Swirl2011-10-231-2/+2
| | | | | | | | | Make raise_exception() and helper_debug() take a parameter for CPUState instead of relying on global env. Move the functions to helper.c. Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
* SPARC64: fix VIS1 SIMD signed compare instructionsTsuneo Saito2011-07-201-2/+2
| | | | | | | | | The destination registers of SIMD signed compare instructions (fcmp*<16|32>) are not FP registers but general purpose r registers. Comparisons should be freg_rs1 CMP freg_rs2, that were reversed. Signed-off-by: Tsuneo Saito <tsnsaito@gmail.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
* Delete unused tb_invalidate_page_rangeBlue Swirl2011-05-221-1/+0Star
| | | | | | | | | | | | tb_invalidate_page_range() was intended to be used to invalidate an area of a TB which the guest explicitly flushes from i-cache. However, QEMU detects writes to code areas where TBs have been generated, so his has never been useful. Delete the function, adjust callers. Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
* SPARC: Emulation of Leon3Fabien Chouteau2011-01-241-0/+1
| | | | | | | | | | | | Leon3 is an open-source VHDL System-On-Chip, well known in space industry (more information on http://www.gaisler.com). Leon3 is made of multiple components available in the GrLib VHDL library. Three devices are implemented: uart, timers and IRQ manager. You can find code for these peripherals in the grlib_* files. Signed-off-by: Fabien Chouteau <chouteau@adacore.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
* target-sparc: fix udiv(cc) and sdiv(cc)Aurelien Jarno2010-12-281-0/+2
| | | | | | | | | | | | | Since commit 5a4bb580cdb10b066f9fd67658b31cac4a4ea5e5, Xorg crashes on a Debian Etch image. The commit itself is fine, but it triggers a bug due to wrong computation of flags for udiv(cc) and sdiv(cc). This patch only compute cc_src2 for the cc version of udiv/sdiv. It also moves the update of cc_dst and cc_op to the helper, as it is faster doing it here when there is already an helper. Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
* target-sparc: Inline some generation of carry for ADDX/SUBX.Richard Henderson2010-05-201-1/+1
| | | | | | | | | | | Computing carry is trivial for some inputs. By avoiding an external function call, we generate near-optimal code for the common cases of add+addx (double-word arithmetic) and cmp+addx (a setcc pattern). Signed-off-by: Richard Henderson <rth@twiddle.net> Acked-by: Artyom Tarasenko <atar4qemu@gmail.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
* target-sparc: Fix compilation with --enable-debug.Richard Henderson2010-05-191-1/+1
| | | | | | | Return a target_ulong from compute_C_icc to match the width of the users. Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
* sparc64: use helper_wrpil to check pending irq on writeIgor V. Kovalenko2010-01-081-0/+1
| | | | | Signed-off-by: Igor V. Kovalenko <igor.v.kovalenko@gmail.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
* Use dynamical computation for condition codesBlue Swirl2009-05-101-0/+2
| | | | Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
* TCG variable type checking.pbrook2008-11-171-109/+101Star
| | | | | | | Signed-off-by: Paul Brook <paul@codesourcery.com> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5729 c046a42c-6fe2-441c-8c8c-71466251a162
* Implement UA2005 hypervisor trapsblueswir12008-09-261-2/+0Star
| | | | git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5327 c046a42c-6fe2-441c-8c8c-71466251a162
* Add software and timer interrupt supportblueswir12008-09-221-0/+3
| | | | git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5299 c046a42c-6fe2-441c-8c8c-71466251a162
* Use the new concat_i32_i64 op for std and stdablueswir12008-09-211-1/+0Star
| | | | git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5281 c046a42c-6fe2-441c-8c8c-71466251a162
* Convert rest of ops using float32 to TCG, remove FT0 and FT1blueswir12008-09-101-11/+8Star
| | | | git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5193 c046a42c-6fe2-441c-8c8c-71466251a162
* Partially convert float128 conversion ops to TCGblueswir12008-09-101-4/+5
| | | | git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5192 c046a42c-6fe2-441c-8c8c-71466251a162
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