| Commit message (Expand) | Author | Age | Files | Lines |
|---|
| * | target-tricore: Add ftoi and itof instructions | Bastian Koppelmann | 2016-03-23 | 1 | -0/+2 |
| * | target-tricore: Add cmp.f instruction | Bastian Koppelmann | 2016-03-23 | 1 | -0/+1 |
| * | target-tricore: Add div.f instruction | Bastian Koppelmann | 2016-03-23 | 1 | -0/+1 |
| * | target-tricore: Add mul.f instruction | Bastian Koppelmann | 2016-03-23 | 1 | -0/+1 |
| * | target-tricore: add add.f/sub.f instructions | Bastian Koppelmann | 2016-03-23 | 1 | -0/+2 |
| * | target-tricore: Add trap handling & SOVF/OVF traps | Bastian Koppelmann | 2016-02-25 | 1 | -0/+3 |
| * | target-tricore: add RR_DIV and RR_DIV_U instructions of the v1.6 ISA | Bastian Koppelmann | 2015-05-22 | 1 | -0/+2 |
| * | target-tricore: add RR_CRC32 instruction of the v1.6.1 ISA | Bastian Koppelmann | 2015-05-22 | 1 | -0/+2 |
| * | target-tricore: Add instructions of SYS opcode format | Bastian Koppelmann | 2015-03-16 | 1 | -0/+3 |
| * | target-tricore: Add instructions of RRR1 opcode format, which have 0xe3 as fi... | Bastian Koppelmann | 2015-03-16 | 1 | -0/+2 |
| * | target-tricore: Add instructions of RRR1 opcode format, which have 0x63 as fi... | Bastian Koppelmann | 2015-03-16 | 1 | -0/+4 |
| * | target-tricore: Add instructions of RRR1 opcode format, which have 0xa3 as fi... | Bastian Koppelmann | 2015-03-16 | 1 | -0/+3 |
| * | target-tricore: Add instructions of RRR1 opcode format, which have 0xc3 as fi... | Bastian Koppelmann | 2015-03-03 | 1 | -0/+2 |
| * | target-tricore: Add instructions of RRR1 opcode format, which have 0x43 as fi... | Bastian Koppelmann | 2015-03-03 | 1 | -0/+4 |
| * | target-tricore: Add instructions of RRR1 opcode format, which have 0x83 as fi... | Bastian Koppelmann | 2015-03-03 | 1 | -0/+3 |
| * | target-tricore: Add instructions of RRR opcode format | Bastian Koppelmann | 2015-01-27 | 1 | -0/+8 |
| * | target-tricore: Add instructions of RR1 opcode format, that have 0xb3 as firs... | Bastian Koppelmann | 2014-12-21 | 1 | -0/+4 |
| * | target-tricore: Add instructions of RR opcode format, that have 0x4b as the f... | Bastian Koppelmann | 2014-12-21 | 1 | -0/+11 |
| * | target-tricore: Add instructions of RR opcode format, that have 0xf as the fi... | Bastian Koppelmann | 2014-12-21 | 1 | -0/+12 |
| * | target-tricore: Add instructions of RR opcode format, that have 0xb as the fi... | Bastian Koppelmann | 2014-12-21 | 1 | -0/+32 |
| * | target-tricore: Add instructions of RCR opcode format | Bastian Koppelmann | 2014-12-10 | 1 | -0/+8 |
| * | target-tricore: Add instructions of RLC opcode format | Bastian Koppelmann | 2014-12-10 | 1 | -0/+3 |
| * | target-tricore: Add instructions of RC opcode format | Bastian Koppelmann | 2014-12-10 | 1 | -0/+6 |
| * | target-tricore: Add instructions of BO opcode format | Bastian Koppelmann | 2014-10-20 | 1 | -0/+3 |
| * | target-tricore: Add instructions of ABS, ABSB opcode format | Bastian Koppelmann | 2014-10-20 | 1 | -0/+4 |
| * | target-tricore: Add instructions of SR opcode format | Bastian Koppelmann | 2014-09-01 | 1 | -0/+1 |
| * | target-tricore: Add instructions of SC opcode format | Bastian Koppelmann | 2014-09-01 | 1 | -0/+1 |
| * | target-tricore: Add instructions of SB opcode format | Bastian Koppelmann | 2014-09-01 | 1 | -0/+3 |
| * | target-tricore: Add instructions of SRR opcode format | Bastian Koppelmann | 2014-09-01 | 1 | -0/+4 |
| * | target-tricore: Add instructions of SRC opcode format | Bastian Koppelmann | 2014-09-01 | 1 | -0/+16 |
| * | target-tricore: Add target stubs and qom-cpu | Bastian Koppelmann | 2014-09-01 | 1 | -0/+0 |
