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* disas: Remove uses of CPU envPeter Crosthwaite2015-06-221-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | disas does not need to access the CPU env for any reason. Change the APIs to accept CPU pointers instead. Small change pattern needs to be applied to all target translate.c. This brings us closer to making disas.o a common-obj and less architecture specific in general. Cc: Richard Henderson <rth@twiddle.net> Cc: Peter Maydell <peter.maydell@linaro.org> Cc: "Edgar E. Iglesias" <edgar.iglesias@gmail.com> Cc: Paolo Bonzini <pbonzini@redhat.com> Cc: Eduardo Habkost <ehabkost@redhat.com> Cc: Michael Walle <michael@walle.cc> Cc: Aurelien Jarno <aurelien@aurel32.net> Cc: Leon Alrae <leon.alrae@imgtec.com> Cc: Jia Liu <proljc@gmail.com> Cc: Alexander Graf <agraf@suse.de> Cc: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Cc: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Cc: Guan Xuetao <gxt@mprc.pku.edu.cn> Cc: Max Filippov <jcmvbkbc@gmail.com> Reviewed-by: Richard Henderson <rth@twiddle.net> Reviewed-by: Eduardo Habkost <ehabkost@redhat.com> Signed-off-by: Peter Crosthwaite <crosthwaite.peter@gmail.com> Acked-by: Luiz Capitulino <lcapitulino@redhat.com> Signed-off-by: Markus Armbruster <armbru@redhat.com>
* target-tricore: fix BOL_ST_H_LONGOFF using ldBastian Koppelmann2015-05-301-1/+1
| | | | | Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Message-Id: <1432289758-6250-4-git-send-email-kbastian@mail.uni-paderborn.de>
* target-tricore: fix msub32_q producing the wrong overflow bitBastian Koppelmann2015-05-301-11/+0Star
| | | | | | | | The inversion of the overflow bit as a special case, which was needed for the madd32_q instructions, does not apply for msub32_q instructions. So remove it. Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Message-Id: <1432289758-6250-3-git-send-email-kbastian@mail.uni-paderborn.de>
* target-tricore: fix OPC2_32_RR_DVINIT_HU having write before use on the resultBastian Koppelmann2015-05-301-1/+1
| | | | | | | | If the argument r1 was the same as the extended result register r3+1, we would overwrite r1 and then use it. Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Message-Id: <1432289758-6250-2-git-send-email-kbastian@mail.uni-paderborn.de>
* target-tricore: add RR_DIV and RR_DIV_U instructions of the v1.6 ISABastian Koppelmann2015-05-224-0/+74
| | | | | Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Reviewed-by: Richard Henderson <rth@twiddle.net>
* target-tricore: add FRET instructions of the v1.6 ISABastian Koppelmann2015-05-222-0/+21
| | | | | Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Reviewed-by: Richard Henderson <rth@twiddle.net>
* target-tricore: add FCALL instructions of the v1.6 ISABastian Koppelmann2015-05-222-0/+29
| | | | | Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Reviewed-by: Richard Henderson <rth@twiddle.net>
* target-tricore: add SYS_RESTORE instruction of the v1.6 ISABastian Koppelmann2015-05-222-0/+11
| | | | | Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Reviewed-by: Richard Henderson <rth@twiddle.net>
* target-tricore: add RR_CRC32 instruction of the v1.6.1 ISABastian Koppelmann2015-05-224-0/+19
| | | | | | | This instruction was introduced by the new Aurix platform. Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Reviewed-by: Richard Henderson <rth@twiddle.net>
* target-tricore: add SWAPMSK instructions of the v1.6.1 ISABastian Koppelmann2015-05-222-0/+44
| | | | | | | Those instruction were introduced in the new Aurix platform. Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Reviewed-by: Richard Henderson <rth@twiddle.net>
* target-tricore: add CMPSWP instructions of the v1.6.1 ISABastian Koppelmann2015-05-222-0/+40
| | | | | | | Those instruction were introduced in the new Aurix platform. Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Reviewed-by: Richard Henderson <rth@twiddle.net>
* target-tricore: Add SRC_MOV_E instruction of the v1.6 ISABastian Koppelmann2015-05-221-2/+9
| | | | | Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Reviewed-by: Richard Henderson <rth@twiddle.net>
* target-tricore: introduce ISA v1.6.1 featureBastian Koppelmann2015-05-222-3/+8
| | | | | | | | | The aurix platform contains of several different cpu models and uses the 1.6.1 ISA. This patch changes the generic aurix model to the more specific tc27x cpu model and sets specific features. Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Reviewed-by: Richard Henderson <rth@twiddle.net>
* target-tricore: Add ISA v1.3.1 cpu and fix tc1796 to using v1.3Bastian Koppelmann2015-05-221-0/+8
| | | | | Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Reviewed-by: Richard Henderson <rth@twiddle.net>
* target-tricore: fix rfe not restoring the PCBastian Koppelmann2015-05-111-0/+1
| | | | Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
* target-tricore: fix rslcx restoring the upper context instead of the lowerBastian Koppelmann2015-05-111-1/+1
| | | | Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
* target-tricore: fix BO_OFF10_SEXT calculating the wrong offsetBastian Koppelmann2015-05-111-1/+1
| | | | | | | The lower part of the combined offset was sign extended and could lead to wrong results. Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
* target-tricore: fix SLR_LD_W and SLR_LD_W_POSTINC insn being a 2 byte memory ↵Bastian Koppelmann2015-05-111-2/+2
| | | | | | access insted of 4 Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
* target-tricore: Fix LOOP using wrong register for compareBastian Koppelmann2015-05-111-1/+1
| | | | Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
* tcg: Delete unused cpu_pc_from_tb()Peter Crosthwaite2015-04-301-5/+0Star
| | | | | | | | | No code uses the cpu_pc_from_tb() function. Delete from tricore and arm which each provide an unused implementation. Update the comment in tcg.h to reflect that this is obsoleted by synchronize_from_tb. Signed-off-by: Peter Crosthwaite <crosthwaite.peter@gmail.com> Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
* target-tricore: Fix check which was always falseStefan Weil2015-04-041-1/+1
| | | | | | | | With a mask value of 0x00400000, the result will never be 1. This fixes a Coverity warning. Signed-off-by: Stefan Weil <sw@weilnetz.de> Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
* target-tricore: fix CACHEA/I_POSTINC/PREINC using data register..Bastian Koppelmann2015-03-301-4/+4
| | | | | | ..for address calculation instead address registers. Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
* target-tricore: properly fix dvinit_b/h_13Bastian Koppelmann2015-03-241-30/+10Star
| | | | | | | | The TriCore documentation was wrong on how to calculate ovf bits for those two instructions, which I confirmed with real hardware (TC1796 chip). An ovf actually happens, if the result (without remainder) does not fit into 8/16 bits. Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
* target-tricore: fix RRPW_DEXTR using wrong regBastian Koppelmann2015-03-241-2/+2
| | | | | | | | | RRPW_DEXTR used r1 for the low part and r2 for the high part. It should be the other way round. This also fixes that the result of the first shift was not saved in a temp and could overwrite registers that were needed for the second shift. Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
* target-tricore: fix DVINIT_HU/BU calculating overflow before resultBastian Koppelmann2015-03-241-12/+18
| | | | | | | dvinit_hu/bu for ISA v1.3 calculate the higher part of the result, that is needed for the overflow bits, after calculating the overflow bits. Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
* target-tricore: Fix two helper functions (clang warnings)Stefan Weil2015-03-241-6/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | clang report: target-tricore/op_helper.c:1247:24: warning: taking the absolute value of unsigned type 'uint32_t' (aka 'unsigned int') has no effect [-Wabsolute-value] target-tricore/op_helper.c:1248:25: warning: taking the absolute value of unsigned type 'uint32_t' (aka 'unsigned int') has no effect [-Wabsolute-value] target-tricore/op_helper.c:1249:19: warning: taking the absolute value of unsigned type 'uint32_t' (aka 'unsigned int') has no effect [-Wabsolute-value] target-tricore/op_helper.c:1297:24: warning: taking the absolute value of unsigned type 'uint32_t' (aka 'unsigned int') has no effect [-Wabsolute-value] target-tricore/op_helper.c:1298:25: warning: taking the absolute value of unsigned type 'uint32_t' (aka 'unsigned int') has no effect [-Wabsolute-value] target-tricore/op_helper.c:1299:19: warning: taking the absolute value of unsigned type 'uint32_t' (aka 'unsigned int') has no effect [-Wabsolute-value] Fix also the divisor which was taken from the wrong register (thanks to Peter Maydell for this hint). Cc: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Signed-off-by: Stefan Weil <sw@weilnetz.de> Message-Id: <1425739412-8144-1-git-send-email-sw@weilnetz.de> Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
* Fix typos in commentsViswesh2015-03-191-11/+11
| | | | | | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Viswesh <visweshn92@gmail.com> Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
* target-tricore: Add instructions of SYS opcode formatBastian Koppelmann2015-03-164-0/+175
| | | | | | This adds only the non trap instructions. Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
* target-tricore: Add instructions of RRRW opcode formatBastian Koppelmann2015-03-161-0/+63
| | | | | Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
* target-tricore: Add instructions of RRRR opcode formatBastian Koppelmann2015-03-161-0/+56
| | | | | Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
* target-tricore: Add instructions of RRR1 opcode format, which have 0xe3 as ↵Bastian Koppelmann2015-03-164-2/+415
| | | | | | | | | | | | | | | | | | | | | | | first opcode Add helpers helper_subadr_h/_ssov which subs one halfword and adds one halfword, rounds / and saturates each half word independently. Add microcode helper functions: * gen_msubad_h/ads_h: multiply two halfwords left justified and sub from the first one word and add the second one word / and saturate each resulting word independetly. * gen_msubadm_h/adms_h: multiply two halfwords in q-format left justified and sub from the first one word and add to the second one word / and saturate each resulting word independetly. * gen_msubadr32_h/32s_h: multiply two halfwords in q-format left justified and sub from the first one word and add to the second one word, round both results / and saturate each resulting word independetly. Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
* target-tricore: Add instructions of RRR1 opcode format, which have 0x63 as ↵Bastian Koppelmann2015-03-164-2/+600
| | | | | | | | | | | | | | | | | first opcode Add helpers: * msub64_q_ssov: multiply two 32 bit q-format number, sub the result from a 64 bit q-format number and saturate. * msub32_q_sub_ssov: sub two 64 bit q-format numbers and return a 32 bit result. * msubr_q_ssov: multiply two 32 bit q-format numbers, sub the result from a 32 bit q-format number and saturate. * msubr_q: multiply two 32 bit q-format numbers and sub the result from a 32 bit q-format number. Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
* target-tricore: Add instructions of RRR1 opcode format, which have 0xa3 as ↵Bastian Koppelmann2015-03-164-24/+493
| | | | | | | | | | | | | | | | | | | | | | | first opcode Add helpers: * sub64_ssov: subs two 64 bit values and saturates the result. * subr_h/_ssov: subs two halfwords from two words in q-format with rounding / and saturates each result independetly. Add microcode generator: * gen_sub64_d: adds two 64 bit values. * gen_msub_h/s_h: multiply four halfwords, sub each result left justfied from two word values / and saturate each result. * gen_msubm_h/s_h: multiply four halfwords, sub each result left justfied from two words values in q-format / and saturate each result. * gen_msubr32/64_h/s_h: multiply four halfwords, sub each result left justfied from two halftwords/words values in q-format / and saturate each result. Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
* tcg: Change translator-side labels to a pointerRichard Henderson2015-03-131-4/+2Star
| | | | | | | | | | | | | | | | | | | | | | | | | | This is improved type checking for the translators -- it's no longer possible to accidentally swap arguments to the branch functions. Note that the code generating backends still manipulate labels as int. With notable exceptions, the scope of the change is just a few lines for each target, so it's not worth building extra machinery to do this change in per-target increments. Cc: Peter Maydell <peter.maydell@linaro.org> Cc: Edgar E. Iglesias <edgar.iglesias@gmail.com> Cc: Michael Walle <michael@walle.cc> Cc: Leon Alrae <leon.alrae@imgtec.com> Cc: Anthony Green <green@moxielogic.com> Cc: Jia Liu <proljc@gmail.com> Cc: Alexander Graf <agraf@suse.de> Cc: Aurelien Jarno <aurelien@aurel32.net> Cc: Blue Swirl <blauwirbel@gmail.com> Cc: Guan Xuetao <gxt@mprc.pku.edu.cn> Cc: Paolo Bonzini <pbonzini@redhat.com> Cc: Max Filippov <jcmvbkbc@gmail.com> Reviewed-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Signed-off-by: Richard Henderson <rth@twiddle.net>
* cpu: Make cpu_init() return QOM CPUState objectEduardo Habkost2015-03-101-9/+1Star
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Instead of making cpu_init() return CPUArchState, return CPUState. Changes were made using the Coccinelle semantic patch below. @@ typedef CPUState; identifier e; expression args; type CPUArchState; @@ - e = + cpu = cpu_init(args); - if (!e) { + if (!cpu) { ... } - cpu = ENV_GET_CPU(env); + e = cpu->env_ptr; @@ identifier new_env, new_cpu, env, cpu; type CPUArchState; expression args; @@ -{ - CPUState *cpu = ENV_GET_CPU(env); - CPUArchState *new_env = cpu_init(args); - CPUState *new_cpu = ENV_GET_CPU(new_env); +{ + CPUState *cpu = ENV_GET_CPU(env); + CPUState *new_cpu = cpu_init(args); + CPUArchState *new_env = new_cpu->env_ptr; ... } @@ identifier c, cpu_init_func, cpu_model; type StateType, CPUType; @@ -static inline StateType* cpu_init(const char *cpu_model) -{ - CPUType *c = cpu_init_func(cpu_model); ( - if (c == NULL) { - return NULL; - } - return &c->env; | - if (c) { - return &c->env; - } - return NULL; ) -} +#define cpu_init(cpu_model) CPU(cpu_init_func(cpu_model)) @@ identifier cpu_init_func; identifier model; @@ -#define cpu_init(model) (&cpu_init_func(model)->env) +#define cpu_init(model) CPU(cpu_init_func(model)) Signed-off-by: Eduardo Habkost <ehabkost@redhat.com> Cc: Blue Swirl <blauwirbel@gmail.com> Cc: Guan Xuetao <gxt@mprc.pku.edu.cn> Cc: Riku Voipio <riku.voipio@iki.fi> Cc: Richard Henderson <rth@twiddle.net> Cc: Peter Maydell <peter.maydell@linaro.org> Cc: "Edgar E. Iglesias" <edgar.iglesias@gmail.com> Cc: Paolo Bonzini <pbonzini@redhat.com> Cc: Michael Walle <michael@walle.cc> Cc: Aurelien Jarno <aurelien@aurel32.net> Cc: Leon Alrae <leon.alrae@imgtec.com> Cc: Anthony Green <green@moxielogic.com> Cc: Jia Liu <proljc@gmail.com> Cc: Alexander Graf <agraf@suse.de> Cc: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Cc: Max Filippov <jcmvbkbc@gmail.com> [AF: Fixed up cpu_copy() manually] Signed-off-by: Andreas Färber <afaerber@suse.de>
* target-tricore: Add instructions of RRR1 opcode format, which have 0xc3 as ↵Bastian Koppelmann2015-03-033-0/+418
| | | | | | | | | | | | | | | | | | | | | | | first opcode Add helpers helper_addsur_h/_ssov which adds one halfword and subtracts one halfword, rounds / and saturates each half word independently. Add microcode helper functions: * gen_maddsu_h/sus_h: multiply two halfwords left justified and add to the first one word and subtract from the second one word / and saturate each resulting word independetly. * gen_maddsum_h/sums_h: multiply two halfwords in q-format left justified and add to the first one word and subtract from the second one word / and saturate each resulting word independetly. * gen_maddsur32_h/32s_h: multiply two halfwords in q-format left justified and add to the first one word and subtract from the second one word, round both results / and saturate each resulting word independetly. Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Reviewed-by: Richard Henderson <rth@twiddle.net>
* target-tricore: Add instructions of RRR1 opcode format, which have 0x43 as ↵Bastian Koppelmann2015-03-034-4/+588
| | | | | | | | | | | | | | | | | | | | | | | first opcode Add helpers: * madd64_q_ssov: multiply two 32 bit q-format number, add them with a 64 bit q-format number and saturate. * madd32_q_add_ssov: add two 64 bit q-format numbers and return a 32 bit result. * maddr_q_ssov: multiplay two 32 bit q-format numbers, add a 32 bit q-format number and saturate. * maddr_q: multiplay two 32 bit q-format numbers and add a 32 bit q-format number. Note: madd instructions in the q format can behave strange, e.g. 0x1 + (0x80000000 * 0x80000000) << 1 for 32 bit signed values does not cause an overflow on the guest, because all intermediate results should be handled as if they are indefinitely precise. We handle this by inverting the overflow bit for all cases: a + (0x80000000 * 0x80000000) << 1. Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Reviewed-by: Richard Henderson <rth@twiddle.net>
* target-tricore: Add instructions of RRR1 opcode format, which have 0x83 as ↵Bastian Koppelmann2015-03-033-0/+534
| | | | | | | | | | | | | | | | | | | | | | | | | first opcode Add helpers: * add64_ssov: adds two 64 bit values and saturates the result. * addr_h/_ssov: adds two halfwords with two words in q-format with rounding / and saturates each result independetly. Add microcode generator: * gen_add64_d: adds two 64 bit values. * gen_addsub64_h: adds/subtracts one halfwords with a word and adds/ subtracts another halftword with another word. * gen_madd_h/s_h: multiply four halfwords, add each result left justfied to two word values / and saturate each result. * gen_maddm_h/s_h: multiply four halfwords, add each result left justfied to two words values in q-format / and saturate each result. * gen_maddr32/64_h/s_h: multiply four halfwords, add each result left justfied to two halftwords/words values in q-format / and saturate each result. Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Reviewed-by: Richard Henderson <rth@twiddle.net>
* target-tricore: Add instructions of RRR2 opcode formatBastian Koppelmann2015-03-032-15/+136
| | | | | Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Reviewed-by: Richard Henderson <rth@twiddle.net>
* target-tricore: fix msub32_suov return wrong resultsBastian Koppelmann2015-03-031-6/+21
| | | | | | | | | | | If the signed result of the multiplication overflows, we would get a negative value, which would result in a addition instead of a subtraction. Now we do the overflow calculation and saturation by hand instead of using suov32_neg. Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Reviewed-by: Richard Henderson <rth@twiddle.net>
* target-tricore: Fix RLC_ADDI, RLC_ADDIH using wrong microcode helperBastian Koppelmann2015-03-031-2/+2
| | | | | Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Reviewed-by: Richard Henderson <rth@twiddle.net>
* tcg: Introduce tcg_op_buf_count and tcg_op_buf_fullRichard Henderson2015-02-131-3/+1Star
| | | | | | | | The method by which we count the number of ops emitted is going to change. Abstract that away into some inlines. Reviewed-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Signed-off-by: Richard Henderson <rth@twiddle.net>
* tcg: Move emit of INDEX_op_end into gen_tb_endRichard Henderson2015-02-131-1/+0Star
| | | | | Reviewed-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Signed-off-by: Richard Henderson <rth@twiddle.net>
* target-tricore: Add instructions of RRR opcode formatBastian Koppelmann2015-01-274-1/+319
| | | | | | | | | | | | | | | | | Add microcode generator function gen_cond_sub. Add helper functions: * ixmax/ixmin: search for the max/min value and its related index in a vector of 16-bit values. * pack: dack two data registers into an IEEE-754 single precision floating point format number. * dvadj: divide-adjust the result after dvstep instructions. * dvstep: divide a reg by a divisor, producing 8-bits of quotient at a time. OPCM_32_RRR_FLOAT -> OPCM_32_RRR_DIVIDE Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Reviewed-by: Richard Henderson <rth@twiddle.net>
* target-tricore: Add instructions of RRPW opcode formatBastian Koppelmann2015-01-271-0/+70
| | | | | Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Reviewed-by: Richard Henderson <rth@twiddle.net>
* target-tricore: Add instructions of RR2 opcode formatBastian Koppelmann2015-01-271-0/+37
| | | | | Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Reviewed-by: Richard Henderson <rth@twiddle.net>
* target-tricore: Add instructions of RR1 opcode format, that have 0x93 as ↵Bastian Koppelmann2015-01-271-0/+182
| | | | | | | first opcode Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Reviewed-by: Richard Henderson <rth@twiddle.net>
* target-tricore: split up suov32 into suov32_pos and suov32_negBastian Koppelmann2015-01-261-15/+26
| | | | | | | | | | | | | | | | | suov checks unsigned for an overflow and an underflow, after some arithmetic operations and saturates the result to either max_uint32 or 0. So far we handled this by expanding to the next bigger data type and compare whether the result is > max_uint32 or < 0. However this approach can fail for an 32 bit multiplication, if both operands of the multiplication are 0x80000000. This sets the sign bit of the 64 bit integer and would result in a false saturation to 0. Since unsigned operations, e.g add, sub, mul always result in either a positive or negative overflow, we split the functions for suov32 up into two functions (suov32_pos, suov32_neg) for each case. Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
* target-tricore: Fix bugs found by coverityBastian Koppelmann2015-01-262-1/+3
| | | | | | | | | | | | This fixes one bug and one false positive found by coverity. The bug is, that gen_mtcr was missing a mask to check the flag, which resulted in dead code. The false positive is a intentional missing break for a jump and link address insn followed by a jump and link insn. This adds a fall through comment to avoid the false positive in the future. Reported-by: Markus Armbruster <armbru@redhat.com> Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
* target-tricore: calculate av bits before saturationBastian Koppelmann2015-01-261-12/+16
| | | | | | | | 64 bit mac instructions calculated the av bits after the saturation, which resulted in a wrong PSW. This moves the av bit calculation before the saturation. Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
generated by cgit v1.2.3-55-g7522 (git 2.39.0) at 2024-12-22 20:44:59 +0100