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path: root/target-xtensa/cpu.h
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* cpu: Make cpu_init() return QOM CPUState objectEduardo Habkost2015-03-101-8/+1Star
* exec.c: Drop TARGET_HAS_ICE define and checksPeter Maydell2015-01-201-2/+0Star
* target-xtensa: record available window in TB flagsMax Filippov2014-12-171-0/+12
* target-xtensa: add missing window check for entryMax Filippov2014-11-101-0/+6
* target-xtensa: add definition for XTHAL_INTTYPE_PROFILINGMax Filippov2014-11-021-0/+1
* cpu-exec: Make debug_excp_handler a QOM CPU methodPeter Maydell2014-09-121-1/+1
* softmmu: move ALIGNED_ONLY to cpu.hPaolo Bonzini2014-06-051-0/+1
* cpu: Move watchpoint fields from CPU_COMMON to CPUStateAndreas Färber2014-03-131-1/+1
* cpu: Turn cpu_has_work() into a CPUClass hookAndreas Färber2014-03-131-7/+0Star
* target-xtensa: Clean up ENV_GET_CPU() usageAndreas Färber2014-03-131-1/+3
* target-xtensa: provide HW confg ID registersMax Filippov2014-02-241-0/+4
* target-xtensa: avoid double-stopping at breakpointsMax Filippov2013-07-291-0/+4
* cpu: Introduce CPUClass::synchronize_from_tb() for cpu_pc_from_tb()Andreas Färber2013-07-231-5/+0Star
* cpu: Replace do_interrupt() by CPUClass::do_interrupt methodAndreas Färber2013-03-121-1/+0Star
* target-xtensa: Move TCG initialization to XtensaCPU initfnAndreas Färber2013-02-161-0/+1
* exec: move include files to include/exec/Paolo Bonzini2012-12-191-3/+3
* target-xtensa: implement MISC SRMax Filippov2012-12-081-0/+1
* target-xtensa: restrict available SRs by enabled optionsMax Filippov2012-12-081-0/+1
* target-xtensa: implement CACHEATTR SRMax Filippov2012-12-081-0/+2
* target-xtensa: implement ATOMCTL SRMax Filippov2012-12-081-0/+10
* cpus: Pass CPUState to [qemu_]cpu_has_work()Andreas Färber2012-10-311-1/+3
* target-xtensa: implement coprocessor context optionMax Filippov2012-09-221-0/+5
* target-xtensa: add FP registersMax Filippov2012-09-221-0/+3
* target-xtensa: make default CPU depend on target endiannessMax Filippov2012-08-091-0/+6
* target-xtensa: update autorefill TLB entries conditionallyMax Filippov2012-06-091-1/+1
* target-xtensa: extract TLB entry setting methodMax Filippov2012-06-091-0/+3
* target-xtensa: Let cpu_xtensa_init() return XtensaCPUAndreas Färber2012-06-041-3/+13
* target-xtensa: QOM'ify CPU resetAndreas Färber2012-04-141-0/+1
* target-xtensa: QOM'ify CPUAndreas Färber2012-04-141-0/+1
* Rename CPUState -> CPUArchStateAndreas Färber2012-03-141-1/+1
* target-xtensa: Don't overuse CPUStateAndreas Färber2012-03-141-22/+22
* target-xtensa: add DBREAK data breakpointsMax Filippov2012-02-201-0/+12
* target-xtensa: add ICOUNT SR and debug exceptionMax Filippov2012-02-181-0/+6
* target-xtensa: implement instruction breakpointsMax Filippov2012-02-181-0/+9
* target-xtensa: add DEBUGCAUSE SR and configurationMax Filippov2012-02-181-0/+15
* target-xtensa: implement info tlb monitor commandMax Filippov2012-02-171-0/+1
* target-xtensa: extract core configuration from overlayMax Filippov2011-10-161-0/+6
* target-xtensa: implement external interrupt mappingMax Filippov2011-10-161-0/+3
* target-xtensa: increase xtensa options accuracyMax Filippov2011-10-161-1/+5
* target-xtensa: implement MAC16 optionMax Filippov2011-10-151-0/+3
* target-xtensa: fix guest hang on masked CCOMPARE interruptMax Filippov2011-10-151-0/+1
* target-xtensa: implement boolean optionMax Filippov2011-09-101-0/+1
* target-xtensa: implement memory protection optionsMax Filippov2011-09-101-1/+55
* target-xtensa: add gdb supportMax Filippov2011-09-101-0/+14
* target-xtensa: implement relocatable vectorsMax Filippov2011-09-101-0/+2
* target-xtensa: implement CPENABLE and PRID SRsMax Filippov2011-09-101-0/+2
* target-xtensa: implement interrupt optionMax Filippov2011-09-101-1/+44
* target-xtensa: implement extended L32RMax Filippov2011-09-101-0/+6
* target-xtensa: implement loop optionMax Filippov2011-09-101-0/+3
* target-xtensa: implement windowed registersMax Filippov2011-09-101-0/+8
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