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path: root/target-xtensa/translate.c
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* cpu: Move breakpoints field from CPU_COMMON to CPUStateAndreas Färber2014-03-131-2/+3
* target-xtensa: provide HW confg ID registersMax Filippov2014-02-241-2/+7
* target-xtensa: add basic checks to icache opcodesMax Filippov2014-02-241-0/+27
* target-xtensa: add basic checks to dcache opcodesMax Filippov2014-02-241-0/+38
* target-xtensa: add RRRI4 opcode format fieldsMax Filippov2014-02-241-0/+9
* target-xtensa: add in_asm loggingMax Filippov2013-10-151-0/+8
* tcg: Move helper registration into tcg_context_initRichard Henderson2013-10-101-2/+0Star
* tcg: Change tcg_gen_exit_tb argument to uintptr_tRichard Henderson2013-09-021-1/+1
* target-xtensa: check register window inlineMax Filippov2013-07-291-8/+25
* target-xtensa: don't generate dead code to access invalid SRsMax Filippov2013-07-291-13/+18
* target-xtensa: avoid double-stopping at breakpointsMax Filippov2013-07-291-2/+1Star
* cpu: Move singlestep_enabled field from CPU_COMMON to CPUStateAndreas Färber2013-07-231-3/+4
* target-xtensa: Change gen_intermediate_code_internal() arg to XtensaCPUAndreas Färber2013-07-091-4/+5
* target-xtensa: gen_intermediate_code_internal() should be inlinedAndreas Färber2013-07-091-2/+3
* cpu: Turn cpu_dump_{state,statistics}() into CPUState hooksAndreas Färber2013-06-281-2/+4
* gen-icount.h: Rename gen_icount_start/end to gen_tb_start/endPeter Maydell2013-03-031-2/+2
* target-xtensa: Use add2/sub2 for macRichard Henderson2013-02-231-16/+13Star
* target-xtensa: Use mul*2 for mul*hiRichard Henderson2013-02-231-14/+6Star
* target-xtensa: fix search_pc for the last TB opcodeMax Filippov2012-12-221-1/+5
* softmmu: move include files to include/sysemu/Paolo Bonzini2012-12-191-1/+1
* misc: move include files to include/qemu/Paolo Bonzini2012-12-191-1/+1
* exec: move include files to include/exec/Paolo Bonzini2012-12-191-2/+2
* build: kill libdis, move disassemblers to disas/Paolo Bonzini2012-12-191-1/+1
* target-xtensa: use movcond where possibleMax Filippov2012-12-081-50/+42Star
* target-xtensa: implement MISC SRMax Filippov2012-12-081-0/+4
* target-xtensa: better control rsr/wsr/xsr access to SRsMax Filippov2012-12-081-19/+30
* target-xtensa: restrict available SRs by enabled optionsMax Filippov2012-12-081-104/+126
* target-xtensa: implement CACHEATTR SRMax Filippov2012-12-081-0/+1
* target-xtensa: implement ATOMCTL SRMax Filippov2012-12-081-0/+13
* TCG: Use gen_opc_instr_start from context instead of global variable.Evgeny Voevodin2012-12-081-2/+2
* TCG: Use gen_opc_icount from context instead of global variable.Evgeny Voevodin2012-12-081-1/+1
* TCG: Use gen_opc_pc from context instead of global variable.Evgeny Voevodin2012-12-081-2/+2
* TCG: Use gen_opc_buf from context instead of global variable.Evgeny Voevodin2012-11-171-2/+2
* TCG: Use gen_opc_ptr from context instead of global variable.Evgeny Voevodin2012-11-171-3/+3
* target-xtensa: avoid using cpu_single_envBlue Swirl2012-11-101-5/+5
* target-xtensa: de-optimize EXTUIAurelien Jarno2012-10-061-20/+2Star
* Emit debug_insn for CPU_LOG_TB_OP_OPT as well.Richard Henderson2012-09-271-1/+1
* target-xtensa: implement coprocessor context optionMax Filippov2012-09-221-0/+38
* target-xtensa: implement FP1 groupMax Filippov2012-09-221-1/+80
* target-xtensa: implement FP0 conversionsMax Filippov2012-09-221-0/+48
* target-xtensa: implement FP0 arithmeticMax Filippov2012-09-221-1/+60
* target-xtensa: implement LSCX and LSCI groupsMax Filippov2012-09-221-4/+54
* target-xtensa: add FP registersMax Filippov2012-09-221-7/+45
* target-xtensa: don't emit extra tcg_gen_goto_tbMax Filippov2012-09-211-1/+3
* target-xtensa: fix extui shift amountMax Filippov2012-09-211-3/+21
* target-xtensa: fix big-endian BBS/BBC implementationMax Filippov2012-07-281-2/+14
* target-xtensa: switch to AREG0-free modeMax Filippov2012-06-101-30/+34
* target-xtensa: fix CCOUNT for conditional branchesMax Filippov2012-06-091-0/+2
* target-xtensa: fix LOOPNEZ/LOOPGTZ translationMax Filippov2012-04-211-1/+1
* target-xtensa: fix tb invalidation for IBREAK and LOOPMax Filippov2012-04-141-0/+2
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