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* exec: Make ldl_*_phys input an AddressSpaceEdgar E. Iglesias2014-02-111-1/+2
* exec: Make tb_invalidate_phys_addr input an ASEdgar E. Iglesias2014-02-111-1/+2
* target-xtensa: add missing DEBUG section to dc233c configMax Filippov2013-11-081-0/+1
* target-xtensa: add in_asm loggingMax Filippov2013-10-151-0/+8
* tcg: Move helper registration into tcg_context_initRichard Henderson2013-10-101-2/+0Star
* target: Include softmmu_exec.h where forgottenRichard Henderson2013-09-021-0/+1
* tcg: Change tcg_gen_exit_tb argument to uintptr_tRichard Henderson2013-09-021-1/+1
* aio / timers: Switch entire codebase to the new timer APIAlex Bligh2013-08-221-1/+1
* Merge remote-tracking branch 'filippov/tags/20130729-xtensa' into stagingAnthony Liguori2013-08-053-23/+53
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| * target-xtensa: check register window inlineMax Filippov2013-07-291-8/+25
| * target-xtensa: don't generate dead code to access invalid SRsMax Filippov2013-07-291-13/+18
| * target-xtensa: avoid double-stopping at breakpointsMax Filippov2013-07-293-2/+8
| * target-xtensa: add fallthrough markersMax Filippov2013-07-291-0/+2
* | cpu: Partially revert "cpu: Change qemu_init_vcpu() argument to CPUState"Andreas Färber2013-07-291-0/+2
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* cpu: Introduce CPUClass::gdb_{read,write}_register()Andreas Färber2013-07-274-2/+14
* gdbstub: Replace GET_REG*() macros with gdb_get_reg*() functionsAndreas Färber2013-07-271-6/+8
* target-xtensa: Move cpu_gdb_{read,write}_register()Andreas Färber2013-07-271-0/+100
* cpu: Introduce CPUState::gdb_num_regs and CPUClass::gdb_num_core_regsAndreas Färber2013-07-262-0/+11
* target-xtensa: Introduce XtensaCPU subclassesAndreas Färber2013-07-263-12/+47
* exec: Change cpu_memory_rw_debug() argument to CPUStateAndreas Färber2013-07-231-5/+5
* cpu: Turn cpu_get_phys_page_debug() into a CPUClass hookAndreas Färber2013-07-234-5/+10
* cpu: Move singlestep_enabled field from CPU_COMMON to CPUStateAndreas Färber2013-07-231-3/+4
* cpu: Introduce CPUClass::synchronize_from_tb() for cpu_pc_from_tb()Andreas Färber2013-07-231-5/+0Star
* cpu: Introduce CPUClass::set_pc() for gdb_set_cpu_pc()Andreas Färber2013-07-231-0/+8
* target-xtensa: Change gen_intermediate_code_internal() arg to XtensaCPUAndreas Färber2013-07-091-4/+5
* target-xtensa: gen_intermediate_code_internal() should be inlinedAndreas Färber2013-07-091-2/+3
* cpu: Drop unnecessary dynamic casts in *_env_get_cpu()Andreas Färber2013-07-091-1/+1
* cpu: Change qemu_init_vcpu() argument to CPUStateAndreas Färber2013-06-281-3/+0Star
* cpu: Turn cpu_dump_{state,statistics}() into CPUState hooksAndreas Färber2013-06-284-3/+10
* cpu: Replace do_interrupt() by CPUClass::do_interrupt methodAndreas Färber2013-03-124-2/+7
* cpu: Move halted and interrupt_request fields to CPUStateAndreas Färber2013-03-121-1/+4
* gen-icount.h: Rename gen_icount_start/end to gen_tb_start/endPeter Maydell2013-03-031-2/+2
* cpu: Introduce ENV_OFFSET macrosAndreas Färber2013-03-031-0/+1
* target-xtensa: Use add2/sub2 for macRichard Henderson2013-02-231-16/+13Star
* target-xtensa: Use mul*2 for mul*hiRichard Henderson2013-02-231-14/+6Star
* cpu: Add CPUArchState pointer to CPUStateAndreas Färber2013-02-161-0/+2
* target-xtensa: Move TCG initialization to XtensaCPU initfnAndreas Färber2013-02-163-13/+9Star
* target-xtensa: Introduce QOM realizefn for XtensaCPUAndreas Färber2013-02-163-1/+18
* target-xtensa: Mark as unmigratableAndreas Färber2013-02-013-39/+9Star
* target-xtensa: fix search_pc for the last TB opcodeMax Filippov2012-12-221-1/+5
* softmmu: move include files to include/sysemu/Paolo Bonzini2012-12-191-1/+1
* misc: move include files to include/qemu/Paolo Bonzini2012-12-197-7/+7
* qom: move include files to include/qom/Paolo Bonzini2012-12-191-1/+1
* exec: move include files to include/exec/Paolo Bonzini2012-12-198-19/+19
* build: kill libdis, move disassemblers to disas/Paolo Bonzini2012-12-191-1/+1
* exec: refactor cpu_restore_stateBlue Swirl2012-12-161-12/+2Star
* target-xtensa: fix ITLB/DTLB page protection flagsMax Filippov2012-12-151-1/+2
* target-xtensa: use movcond where possibleMax Filippov2012-12-081-50/+42Star
* target-xtensa: implement MISC SRMax Filippov2012-12-083-0/+6
* target-xtensa: better control rsr/wsr/xsr access to SRsMax Filippov2012-12-081-19/+30
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