| Commit message (Expand) | Author | Age | Files | Lines |
|---|
| * | arm tcg cpus: Fix Lesser GPL version number | Chetan Pant | 2020-11-15 | 1 | -1/+1 |
| * | target/arm: Convert A32 coprocessor insns to decodetree | Peter Maydell | 2020-08-24 | 1 | -0/+19 |
| * | target/arm: Convert SVC | Richard Henderson | 2019-09-05 | 1 | -0/+4 |
| * | target/arm: Convert B, BL, BLX (immediate) | Richard Henderson | 2019-09-05 | 1 | -0/+8 |
| * | target/arm: Convert LDM, STM | Richard Henderson | 2019-09-05 | 1 | -0/+6 |
| * | target/arm: Convert MOVW, MOVT | Richard Henderson | 2019-09-05 | 1 | -0/+6 |
| * | target/arm: Convert Signed multiply, signed and unsigned divide | Richard Henderson | 2019-09-05 | 1 | -0/+22 |
| * | target/arm: Convert packing, unpacking, saturation, and reversal | Richard Henderson | 2019-09-05 | 1 | -0/+32 |
| * | target/arm: Convert Parallel addition and subtraction | Richard Henderson | 2019-09-05 | 1 | -0/+44 |
| * | target/arm: Convert USAD8, USADA8, SBFX, UBFX, BFC, BFI, UDF | Richard Henderson | 2019-09-05 | 1 | -0/+20 |
| * | target/arm: Convert Synchronization primitives | Richard Henderson | 2019-09-05 | 1 | -0/+48 |
| * | target/arm: Convert load/store (register, immediate, literal) | Richard Henderson | 2019-09-05 | 1 | -0/+120 |
| * | target/arm: Convert T32 ADDW/SUBW | Richard Henderson | 2019-09-05 | 1 | -0/+1 |
| * | target/arm: Convert the rest of A32 Miscelaneous instructions | Richard Henderson | 2019-09-05 | 1 | -0/+8 |
| * | target/arm: Convert ERET | Richard Henderson | 2019-09-05 | 1 | -0/+2 |
| * | target/arm: Convert CLZ | Richard Henderson | 2019-09-05 | 1 | -0/+4 |
| * | target/arm: Convert BX, BXJ, BLX (register) | Richard Henderson | 2019-09-05 | 1 | -0/+7 |
| * | target/arm: Convert Cyclic Redundancy Check | Richard Henderson | 2019-09-05 | 1 | -0/+9 |
| * | target/arm: Convert MRS/MSR (banked, register) | Richard Henderson | 2019-09-05 | 1 | -0/+14 |
| * | target/arm: Convert MSR (immediate) and hints | Richard Henderson | 2019-09-05 | 1 | -0/+25 |
| * | target/arm: Convert Halfword multiply and multiply accumulate | Richard Henderson | 2019-09-05 | 1 | -0/+20 |
| * | target/arm: Convert Saturating addition and subtraction | Richard Henderson | 2019-09-05 | 1 | -0/+10 |
| * | target/arm: Convert multiply and multiply accumulate | Richard Henderson | 2019-09-05 | 1 | -0/+17 |
| * | target/arm: Convert Data Processing (immediate) | Richard Henderson | 2019-09-05 | 1 | -0/+29 |
| * | target/arm: Convert Data Processing (reg-shifted-reg) | Richard Henderson | 2019-09-05 | 1 | -0/+27 |
| * | target/arm: Convert Data Processing (register) | Richard Henderson | 2019-09-05 | 1 | -0/+28 |
| * | target/arm: Add stubs for aa32 decodetree | Richard Henderson | 2019-09-05 | 1 | -0/+23 |
