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path: root/target/arm/cpu.c
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* target/arm: Implement debug_check_breakpointRichard Henderson2021-07-211-0/+1
* target/arm: Enable BFloat16 extensionsRichard Henderson2021-06-031-0/+3
* target/arm: Allow board models to specify initial NS VTORPeter Maydell2021-06-031-0/+10
* hw/core: Constify TCGCPUOpsRichard Henderson2021-05-271-1/+1
* cpu: Move CPUClass::get_phys_page_debug to SysemuCPUOpsPhilippe Mathieu-Daudé2021-05-271-1/+1
* cpu: Move CPUClass::asidx_from_attrs to SysemuCPUOpsPhilippe Mathieu-Daudé2021-05-271-1/+1
* cpu: Move CPUClass::write_elf* to SysemuCPUOpsPhilippe Mathieu-Daudé2021-05-271-2/+2
* cpu: Move CPUClass::virtio_is_big_endian to SysemuCPUOpsPhilippe Mathieu-Daudé2021-05-271-1/+1
* cpu: Move CPUClass::vmsd to SysemuCPUOpsPhilippe Mathieu-Daudé2021-05-271-1/+1
* cpu: Introduce SysemuCPUOps structurePhilippe Mathieu-Daudé2021-05-271-0/+8
* cpu: Rename CPUClass vmsd -> legacy_vmsdPhilippe Mathieu-Daudé2021-05-271-1/+1
* target/arm: Enable SVE2 and related extensionsRichard Henderson2021-05-251-0/+2
* Do not include sysemu/sysemu.h if it's not really necessaryThomas Huth2021-05-021-1/+0Star
* target/arm: Make M-profile VTOR loads on reset handle memory aliasingPeter Maydell2021-03-231-1/+1
* target/arm: Restrict v7A TCG cpus to TCG accelPhilippe Mathieu-Daudé2021-03-081-335/+0Star
* target/arm/cpu: Update coding style to make checkpatch.pl happyPhilippe Mathieu-Daudé2021-03-051-4/+8
* target/arm: Restrict v8M IDAU to TCGPhilippe Mathieu-Daudé2021-03-051-7/+0Star
* target/arm: Set ID_PFR2.SSBS to 1 for "max" 32-bit CPURebecca Cran2021-03-051-0/+4
* target/arm: Enable MTE for user-onlyRichard Henderson2021-02-161-0/+15
* target/arm: Use the proper TBI settings for linux-userRichard Henderson2021-02-161-7/+3Star
* target/arm: Set ID_PFR0.DIT to 1 for "max" 32-bit CPURebecca Cran2021-02-111-0/+4
* cpu: tcg_ops: move to tcg-cpu-ops.h, keep a pointer in CPUClassClaudio Fontana2021-02-051-15/+26
* cpu: move debug_check_watchpoint to tcg_opsClaudio Fontana2021-02-051-2/+2
* cpu: move adjust_watchpoint_address to tcg_opsClaudio Fontana2021-02-051-1/+1
* cpu: move do_unaligned_access to tcg_opsClaudio Fontana2021-02-051-1/+1
* cpu: move cc->transaction_failed to tcg_opsClaudio Fontana2021-02-051-2/+2
* cpu: move cc->do_interrupt to tcg_opsClaudio Fontana2021-02-051-2/+2
* cpu: Move debug_excp_handler to tcg_opsEduardo Habkost2021-02-051-1/+1
* cpu: Move tlb_fill to tcg_opsEduardo Habkost2021-02-051-1/+1
* cpu: Move cpu_exec_* to tcg_opsEduardo Habkost2021-02-051-1/+1
* cpu: Move synchronize_from_tb() to tcg_opsEduardo Habkost2021-02-051-1/+3
* cpu: Introduce TCGCpuOperations structEduardo Habkost2021-02-051-1/+1
* target/arm: Implement SCR_EL2.EEL2Rémi Denis-Courmont2021-01-191-1/+1
* target/arm: remove redundant testsRémi Denis-Courmont2021-01-191-4/+4
* target/arm: Add cpu properties to control pauthRichard Henderson2021-01-191-0/+13
* target/arm: Remove timer_del()/timer_deinit() before timer_free()Peter Maydell2021-01-081-2/+0Star
* tcg: Make tb arg to synchronize_from_tb constRichard Henderson2021-01-071-1/+2
* hw/intc/armv7m_nvic: Update FPDSCR masking for v8.1MPeter Maydell2020-12-101-0/+3
* target/arm: Don't clobber ID_PFR1.Security on M-profile coresPeter Maydell2020-12-101-1/+1
* target/arm: Implement FPSCR.LTPSIZE for M-profile LOB extensionPeter Maydell2020-10-201-0/+9
* target/arm: Fix has_vfp/has_neon ID reg squashing for M-profilePeter Maydell2020-10-201-12/+19
* hw/arm/virt: Implement kvm-steal-timeAndrew Jones2020-10-081-0/+8
* target/arm: Move id_pfr0, id_pfr1 into ARMISARegistersPeter Maydell2020-10-011-10/+10
* target/arm: Replace ARM_FEATURE_PXN with ID_MMFR0.VMSA checkPeter Maydell2020-10-011-1/+0Star
* target/arm: Set instance_align on CPUARM TypeInfoRichard Henderson2020-09-181-0/+2
* target/arm: Remove no-longer-reachable 32-bit KVM codePeter Maydell2020-09-141-60/+53Star
* target/arm: Move setting of CPU halted state to generic codeThiago Jung Bauermann2020-09-081-1/+0Star
* target/arm: Move start-powered-off property to generic CPUStateThiago Jung Bauermann2020-09-081-3/+2Star
* target/arm: Enable FP16 in '-cpu max'Peter Maydell2020-09-011-1/+2
* target/arm: Implement FPST_STD_F16 fpstatusPeter Maydell2020-08-241-0/+3
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