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path: root/target/arm/cpu.h
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* target/arm: SCR_EL3.RW is RAO/WI without AArch32 EL[12]Richard Henderson2022-06-101-0/+5
* target/arm: Move arm_debug_target_el to debug_helper.cRichard Henderson2022-06-101-21/+0Star
* target/arm: Remove TBFLAG_ANY.DEBUG_TARGET_ELRichard Henderson2022-06-101-4/+2Star
* target/arm: Move arm_generate_debug_exceptions out of lineRichard Henderson2022-06-101-91/+0Star
* target/arm: Move arm_singlestep_active out of lineRichard Henderson2022-06-101-10/+0Star
* target/arm: Add ID_AA64SMFR0_EL1Richard Henderson2022-06-081-0/+25
* target/arm: Add isar_feature_aa64_smeRichard Henderson2022-06-081-0/+5
* target/arm: Rename sve_zcr_len_for_el to sve_vqm1_for_elRichard Henderson2022-06-081-1/+10
* target/arm: Use uint32_t instead of bitmap for sve vq'sRichard Henderson2022-06-081-3/+3
* linux-user/aarch64: Introduce sve_vqRichard Henderson2022-06-081-0/+11
* target/arm: Rename TBFLAG_A64 ZCR_LEN to VLRichard Henderson2022-06-081-1/+2
* target/arm: Implement FEAT_DoubleFaultPeter Maydell2022-06-081-0/+5
* target/arm: Use FIELD definitions for CPACR, CPTR_ELxRichard Henderson2022-05-191-5/+39
* target/arm: Enable FEAT_HCX for -cpu maxRichard Henderson2022-05-191-0/+20
* target/arm: Make number of counters in PMCR follow the CPUPeter Maydell2022-05-191-0/+1
* hw/intc/arm_gicv3: Use correct number of priority bits for the CPUPeter Maydell2022-05-191-0/+1
* target/arm: Implement FEAT_IDSTPeter Maydell2022-05-191-0/+5
* target/arm: Implement FEAT_S2FWBPeter Maydell2022-05-191-0/+5
* target/arm: Enable FEAT_CSV2_2 for -cpu maxRichard Henderson2022-05-091-0/+16
* target/arm: Implement virtual SError exceptionsRichard Henderson2022-05-091-0/+2
* target/arm: Add minimal RAS registersRichard Henderson2022-05-091-0/+5
* target/arm: Add isar_feature_{aa64,any}_rasRichard Henderson2022-05-051-0/+10
* target/arm: Add isar predicates for FEAT_Debugv8p2Richard Henderson2022-05-051-0/+15
* target/arm: Split out cpregs.hRichard Henderson2022-05-051-368/+0Star
* target/arm: Remove fpexc32_accessRichard Henderson2022-04-221-5/+0Star
* target/arm: Change CPUArchState.thumb to boolRichard Henderson2022-04-221-1/+1
* target/arm: Change CPUArchState.aarch64 to boolRichard Henderson2022-04-221-1/+1
* target/arm: Update SCTLR bits to ARMv9.2Richard Henderson2022-04-221-0/+14
* target/arm: Update SCR_EL3 bits to ARMv8.8Richard Henderson2022-04-221-0/+12
* target/arm: Update ISAR fields for ARMv8.8Richard Henderson2022-04-221-0/+24
* Move CPU softfloat unions to cpu-float.hMarc-André Lureau2022-04-061-0/+1
* Replace TARGET_WORDS_BIGENDIANMarc-André Lureau2022-04-061-4/+4
* Replace config-time define HOST_WORDS_BIGENDIANMarc-André Lureau2022-04-061-4/+4
* target/arm: Make rvbar settable after realizeEdgar E. Iglesias2022-03-181-1/+2
* Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20220307'...Peter Maydell2022-03-081-1/+4
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| * target/arm: Provide cpu property for controling FEAT_LPA2Richard Henderson2022-03-071-1/+4
* | target: Use ArchCPU as interface to target CPUPhilippe Mathieu-Daudé2022-03-061-1/+1
* | target: Introduce and use OBJECT_DECLARE_CPU_TYPE() macroPhilippe Mathieu-Daudé2022-03-061-2/+0Star
* | target: Use CPUArchState as interface to target-specific CPU statePhilippe Mathieu-Daudé2022-03-061-2/+1Star
|/
* target/arm: Implement FEAT_LPA2Richard Henderson2022-03-021-0/+22
* target/arm: Implement FEAT_LVARichard Henderson2022-03-021-0/+5
* hw/arm/virt: KVM: Enable PAuth when supported by the hostMarc Zyngier2022-01-201-0/+1
* include/exec: Move cpu_signal_handler declarationRichard Henderson2021-09-221-7/+0Star
* target/arm: Add TB flag for "MVE insns not predicated"Peter Maydell2021-09-211-1/+3
* hvf: arm: Implement -cpu hostPeter Maydell2021-09-211-0/+2
* target/arm: Restrict cpu_exec_interrupt() handler to sysemuPhilippe Mathieu-Daudé2021-09-141-2/+1Star
* target/arm: Take an exception if PSTATE.IL is setPeter Maydell2021-09-131-0/+1
* target/arm: Do hflags rebuild in cpsr_write()Peter Maydell2021-08-261-2/+8
* target/arm: Implement HSTR.TJDBXPeter Maydell2021-08-261-0/+1
* target/arm: Implement HSTR.TTEEPeter Maydell2021-08-261-0/+2
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