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Experimental fork of QEMU with video encoding patches
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path:
root
/
target
/
arm
/
cpu_tcg.c
Commit message (
Expand
)
Author
Age
Files
Lines
*
target/arm: Set TCGCPUOps.restore_state_to_opc for v7m
Evgeny Ermakov
2022-11-30
1
-0
/
+1
*
target/arm: update the cortex-a15 MIDR to latest rev
Alex Bennée
2022-10-20
1
-1
/
+3
*
target/arm: Report FEAT_PMUv3p5 for TCG '-cpu max'
Peter Maydell
2022-09-14
1
-1
/
+1
*
target/arm: Add missing space in comment
Peter Maydell
2022-09-14
1
-1
/
+1
*
target/arm: Advertise FEAT_ETS for '-cpu max'
Peter Maydell
2022-09-14
1
-0
/
+4
*
target/arm: Implement AArch32 DBGDEVID, DBGDEVID1, DBGDEVID2
Peter Maydell
2022-07-07
1
-0
/
+6
*
target/arm: Make number of counters in PMCR follow the CPU
Peter Maydell
2022-05-19
1
-0
/
+6
*
target/arm: Enable FEAT_CSV3 for -cpu max
Richard Henderson
2022-05-09
1
-0
/
+1
*
target/arm: Enable FEAT_CSV2 for -cpu max
Richard Henderson
2022-05-09
1
-0
/
+1
*
target/arm: Enable FEAT_RAS for -cpu max
Richard Henderson
2022-05-09
1
-0
/
+1
*
target/arm: Enable FEAT_Debugv8p4 for -cpu max
Richard Henderson
2022-05-09
1
-2
/
+2
*
target/arm: Enable FEAT_Debugv8p2 for -cpu max
Richard Henderson
2022-05-09
1
-0
/
+2
*
target/arm: Annotate arm_max_initfn with FEAT identifiers
Richard Henderson
2022-05-09
1
-24
/
+24
*
target/arm: Split out aa32_max_features
Richard Henderson
2022-05-09
1
-53
/
+61
*
target/arm: Set ID_DFR0.PerfMon for qemu-system-arm -cpu max
Richard Henderson
2022-05-09
1
-0
/
+4
*
target/arm: Update qemu-system-arm -cpu max to cortex-a57
Richard Henderson
2022-05-09
1
-60
/
+93
*
target/arm: Move cortex impdef sysregs to cpu_tcg.c
Richard Henderson
2022-05-09
1
-0
/
+59
*
target/arm: Replace sentinels with ARRAY_SIZE in cpregs.h
Richard Henderson
2022-05-05
1
-4
/
+0
*
target/arm: Split out cpregs.h
Richard Henderson
2022-05-05
1
-0
/
+1
*
target/arm: Implement arm_cpu_record_sigbus
Richard Henderson
2021-11-02
1
-0
/
+1
*
target/arm: Implement arm_cpu_record_sigsegv
Richard Henderson
2021-11-02
1
-2
/
+4
*
target/arm: Restrict cpu_exec_interrupt() handler to sysemu
Philippe Mathieu-Daudé
2021-09-14
1
-3
/
+3
*
target/arm: Enable MVE in Cortex-M55
Peter Maydell
2021-09-01
1
-5
/
+2
*
target/arm: Implement debug_check_breakpoint
Richard Henderson
2021-07-21
1
-0
/
+1
*
target/arm: Enable BFloat16 extensions
Richard Henderson
2021-06-03
1
-0
/
+1
*
hw/core: Constify TCGCPUOps
Richard Henderson
2021-05-27
1
-1
/
+1
*
target/arm: Enable SVE2 and related extensions
Richard Henderson
2021-05-25
1
-0
/
+1
*
Revert "target/arm: Make number of counters in PMCR follow the CPU"
Peter Maydell
2021-04-06
1
-5
/
+0
*
target/arm: Make number of counters in PMCR follow the CPU
Peter Maydell
2021-03-30
1
-0
/
+5
*
target/arm: Restrict v7A TCG cpus to TCG accel
Philippe Mathieu-Daudé
2021-03-08
1
-0
/
+318
*
target/arm: Restrict v8M IDAU to TCG
Philippe Mathieu-Daudé
2021-03-05
1
-0
/
+8
*
cpu: tcg_ops: move to tcg-cpu-ops.h, keep a pointer in CPUClass
Claudio Fontana
2021-02-05
1
-5
/
+23
*
cpu: move cc->do_interrupt to tcg_ops
Claudio Fontana
2021-02-05
1
-5
/
+4
*
cpu: Move cpu_exec_* to tcg_ops
Eduardo Habkost
2021-02-05
1
-1
/
+6
*
target/arm: Implement Cortex-M55 model
Peter Maydell
2021-01-08
1
-0
/
+42
*
target/arm: Add ID register values for Cortex-M0
Peter Maydell
2020-10-01
1
-0
/
+24
*
target/arm: Move id_pfr0, id_pfr1 into ARMISARegisters
Peter Maydell
2020-10-01
1
-18
/
+18
*
target/arm: Use correct GDB XML for M-profile cores
Peter Maydell
2020-05-14
1
-0
/
+1
*
target/arm: Restrict TCG cpus to TCG accel
Philippe Mathieu-Daudé
2020-05-11
1
-0
/
+664
