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path: root/target/arm/helper.c
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* target/arm: Implement FEAT_LPA2Richard Henderson2022-03-021-15/+87
* target/arm: Validate tlbi TG matches translation granule in useRichard Henderson2022-03-021-3/+7
* target/arm: Fix TLBIRange.base for 16k and 64k pagesRichard Henderson2022-03-021-2/+3
* target/arm: Introduce tlbi_aa64_get_rangeRichard Henderson2022-03-021-34/+24Star
* target/arm: Implement FEAT_LPARichard Henderson2022-03-021-3/+16
* target/arm: Implement FEAT_LVARichard Henderson2022-03-021-1/+8
* target/arm: Prepare DBGBVR and DBGWVR for FEAT_LVARichard Henderson2022-03-021-8/+24
* target/arm: Honor TCR_ELx.{I}PSRichard Henderson2022-03-021-16/+56
* target/arm: Use MAKE_64BIT_MASK to compute indexmaskRichard Henderson2022-03-021-2/+2
* target/arm: Pass outputsize down to check_s2_mmu_setupRichard Henderson2022-03-021-11/+10Star
* target/arm: Move arm_pamax out of lineRichard Henderson2022-03-021-0/+22
* target/arm: Fault on invalid TCR_ELx.TxSZRichard Henderson2022-03-021-4/+28
* exec/exec-all: Move 'qemu/log.h' include in units requiring itPhilippe Mathieu-Daudé2022-02-211-0/+1
* target: Add missing "qemu/timer.h" includePhilippe Mathieu-Daudé2022-02-211-0/+1
* target/arm: Use CPTR_TFP with CPTR_EL3 in fp_exception_elRichard Henderson2022-02-081-1/+1
* target/arm: Fix {fp, sve}_exception_el for VHE mode runningRichard Henderson2022-02-081-17/+60
* target/arm: Tidy sve_exception_el for CPACR_EL1 accessRichard Henderson2022-02-081-19/+17Star
* target/arm: Fix sve_zcr_len_for_el for VHE mode runningRichard Henderson2022-02-081-1/+2
* target/arm: Use correct entrypoint for SVC taken from Hyp to HypPeter Maydell2022-01-281-2/+2
* target/arm: Log CPU index in 'Taking exception' logPeter Maydell2022-01-281-3/+6
* target/arm: Add missing FEAT_TLBIOS instructionsIdan Horowitz2022-01-071-0/+32
* target/arm: Correct calculation of tlb range invalidate lengthPeter Maydell2021-12-151-3/+3
* target/arm: Move gdbstub related code out of helper.cPeter Maydell2021-09-301-271/+0Star
* target/arm: Fix coding style issues in gdbstub code in helper.cPeter Maydell2021-09-301-7/+16
* target/arm: Add TB flag for "MVE insns not predicated"Peter Maydell2021-09-211-0/+33
* arm: Move PMC register definitions to internals.hAlexander Graf2021-09-201-44/+0Star
* target/arm: Take an exception if PSTATE.IL is setPeter Maydell2021-09-131-0/+8
* target/arm: Do hflags rebuild in cpsr_write()Peter Maydell2021-08-261-0/+5
* target/arm: Implement HSTR.TJDBXPeter Maydell2021-08-261-0/+17
* target/arm: Implement HSTR.TTEEPeter Maydell2021-08-261-2/+16
* target/arm: Implement M-profile trapping on division by zeroPeter Maydell2021-08-251-2/+17
* target/arm: Re-indent sdiv and udiv helpersPeter Maydell2021-08-251-6/+9
* target/arm: Export aarch64_sve_zcr_get_valid_lenRichard Henderson2021-07-271-2/+2
* target/arm: Correctly bound length in sve_zcr_get_valid_lenRichard Henderson2021-07-271-1/+3
* target/arm: Fix offsets for TTBCRRichard Henderson2021-07-181-4/+7
* target/arm: Correct the encoding of MDCCSR_EL0 and DBGDSCRinthnick@vmware.com2021-07-091-3/+13
* target/arm: Add ID_AA64ZFR0 fields and isar_feature_aa64_sve2Richard Henderson2021-05-251-2/+1Star
* target/arm: Add support for FEAT_TLBIOSRebecca Cran2021-05-251-0/+43
* target/arm: Add support for FEAT_TLBIRANGERebecca Cran2021-05-251-0/+281
* target/arm: Fix tlbbits calculation in tlbi_aa64_vae2is_write()Peter Maydell2021-05-101-1/+1
* target/arm: Add ALIGN_MEM to TBFLAG_ANYRichard Henderson2021-04-301-2/+17
* target/arm: Move mode specific TB flags to tb->cs_baseRichard Henderson2021-04-301-4/+6
* target/arm: Introduce CPUARMTBFlagsRichard Henderson2021-04-301-22/+26
* target/arm: Add wrapper macros for accessing tbflagsRichard Henderson2021-04-301-46/+39Star
* target/arm: Rename TBFLAG_ANY, PSTATE_SSRichard Henderson2021-04-301-2/+2
* target/arm: Rename TBFLAG_A32, SCTLR_BRichard Henderson2021-04-301-1/+1
* Revert "target/arm: Make number of counters in PMCR follow the CPU"Peter Maydell2021-04-061-17/+12Star
* target/arm: Make number of counters in PMCR follow the CPUPeter Maydell2021-03-301-12/+17
* semihosting: Move include/hw/semihosting/ -> include/semihosting/Philippe Mathieu-Daudé2021-03-101-2/+2
* target/arm: Use TCF0 and TFSRE0 for unprivileged tag checksPeter Collingbourne2021-03-051-1/+1
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