| Commit message (Expand) | Author | Age | Files | Lines |
|---|
| * | target/arm: Implement MVE VADDLV | Peter Maydell | 2021-07-02 | 1 | -1/+5 |
| * | target/arm: Implement MVE VSHLC | Peter Maydell | 2021-07-02 | 1 | -0/+2 |
| * | target/arm: Implement MVE saturating narrowing shifts | Peter Maydell | 2021-07-02 | 1 | -0/+28 |
| * | target/arm: Implement MVE VSHRN, VRSHRN | Peter Maydell | 2021-07-02 | 1 | -0/+11 |
| * | target/arm: Implement MVE VSRI, VSLI | Peter Maydell | 2021-07-02 | 1 | -0/+9 |
| * | target/arm: Implement MVE VSHLL | Peter Maydell | 2021-07-02 | 1 | -4/+49 |
| * | target/arm: Implement MVE vector shift right by immediate insns | Peter Maydell | 2021-07-02 | 1 | -0/+28 |
| * | target/arm: Implement MVE vector shift left by immediate insns | Peter Maydell | 2021-07-02 | 1 | -0/+23 |
| * | target/arm: Implement MVE logical immediate insns | Peter Maydell | 2021-07-02 | 1 | -0/+17 |
| * | target/arm: Implement MVE VADDV | Peter Maydell | 2021-06-24 | 1 | -0/+2 |
| * | target/arm: Implement MVE VHCADD | Peter Maydell | 2021-06-24 | 1 | -2/+6 |
| * | target/arm: Implement MVE VCADD | Peter Maydell | 2021-06-24 | 1 | -2/+7 |
| * | target/arm: Implement MVE VADC, VSBC | Peter Maydell | 2021-06-24 | 1 | -0/+5 |
| * | target/arm: Implement MVE VRHADD | Peter Maydell | 2021-06-24 | 1 | -0/+3 |
| * | target/arm: Implement MVE VQDMULL (vector) | Peter Maydell | 2021-06-24 | 1 | -0/+5 |
| * | target/arm: Implement MVE VQDMLSDH and VQRDMLSDH | Peter Maydell | 2021-06-24 | 1 | -0/+5 |
| * | target/arm: Implement MVE VQDMLADH and VQRDMLADH | Peter Maydell | 2021-06-24 | 1 | -0/+5 |
| * | target/arm: Implement MVE VRSHL | Peter Maydell | 2021-06-24 | 1 | -0/+3 |
| * | target/arm: Implement MVE VSHL insn | Peter Maydell | 2021-06-24 | 1 | -0/+3 |
| * | target/arm: Implement MVE VQRSHL | Peter Maydell | 2021-06-24 | 1 | -0/+3 |
| * | target/arm: Implement MVE VQSHL (vector) | Peter Maydell | 2021-06-24 | 1 | -0/+12 |
| * | target/arm: Implement MVE VQADD, VQSUB (vector) | Peter Maydell | 2021-06-24 | 1 | -0/+5 |
| * | target/arm: Implement MVE VQDMULH, VQRDMULH (vector) | Peter Maydell | 2021-06-24 | 1 | -0/+3 |
| * | target/arm: Implement MVE VQDMULL scalar | Peter Maydell | 2021-06-24 | 1 | -4/+19 |
| * | target/arm: Implement MVE VQDMULH and VQRDMULH (scalar) | Peter Maydell | 2021-06-24 | 1 | -0/+3 |
| * | target/arm: Implement MVE VQADD and VQSUB | Peter Maydell | 2021-06-24 | 1 | -0/+5 |
| * | target/arm: Implement MVE VPST | Peter Maydell | 2021-06-24 | 1 | -0/+4 |
| * | target/arm: Implement MVE VBRSR | Peter Maydell | 2021-06-24 | 1 | -0/+1 |
| * | target/arm: Implement MVE VHADD, VHSUB (scalar) | Peter Maydell | 2021-06-24 | 1 | -0/+4 |
| * | target/arm: Implement MVE VSUB, VMUL (scalar) | Peter Maydell | 2021-06-24 | 1 | -0/+2 |
| * | target/arm: Implement MVE VADD (scalar) | Peter Maydell | 2021-06-24 | 1 | -0/+7 |
| * | target/arm: Implement MVE VRMLALDAVH, VRMLSLDAVH | Peter Maydell | 2021-06-21 | 1 | -0/+7 |
| * | target/arm: Implement MVE VMLSLDAV | Peter Maydell | 2021-06-21 | 1 | -0/+2 |
| * | target/arm: Implement MVE VMLALDAV | Peter Maydell | 2021-06-21 | 1 | -0/+15 |
| * | target/arm: Implement MVE VMULL | Peter Maydell | 2021-06-21 | 1 | -0/+5 |
| * | target/arm: Implement MVE VHADD, VHSUB | Peter Maydell | 2021-06-21 | 1 | -0/+5 |
| * | target/arm: Implement MVE VABD | Peter Maydell | 2021-06-21 | 1 | -0/+3 |
| * | target/arm: Implement MVE VMAX, VMIN | Peter Maydell | 2021-06-21 | 1 | -0/+5 |
| * | target/arm: Implement MVE VRMULH | Peter Maydell | 2021-06-21 | 1 | -0/+3 |
| * | target/arm: Implement MVE VMULH | Peter Maydell | 2021-06-21 | 1 | -0/+3 |
| * | target/arm: Implement MVE VADD, VSUB, VMUL | Peter Maydell | 2021-06-21 | 1 | -0/+5 |
| * | target/arm: Implement MVE VAND, VBIC, VORR, VORN, VEOR | Peter Maydell | 2021-06-21 | 1 | -0/+9 |
| * | target/arm: Implement MVE VDUP | Peter Maydell | 2021-06-21 | 1 | -0/+10 |
| * | target/arm: Implement MVE VNEG | Peter Maydell | 2021-06-21 | 1 | -0/+2 |
| * | target/arm: Implement MVE VABS | Peter Maydell | 2021-06-21 | 1 | -0/+3 |
| * | target/arm: Implement MVE VMVN (register) | Peter Maydell | 2021-06-21 | 1 | -0/+3 |
| * | target/arm: Implement MVE VREV16, VREV32, VREV64 | Peter Maydell | 2021-06-21 | 1 | -0/+4 |
| * | target/arm: Implement MVE VCLS | Peter Maydell | 2021-06-21 | 1 | -0/+1 |
| * | target/arm: Implement MVE VCLZ | Peter Maydell | 2021-06-21 | 1 | -0/+8 |
| * | target/arm: Implement widening/narrowing MVE VLDR/VSTR insns | Peter Maydell | 2021-06-21 | 1 | -2/+23 |
