| Commit message (Expand) | Author | Age | Files | Lines |
|---|
| * | target/arm: Pass separate addend to FCMLA helpers | Richard Henderson | 2021-05-25 | 1 | -5/+23 |
| * | target/arm: Pass separate addend to {U, S}DOT helpers | Richard Henderson | 2021-05-25 | 1 | -2/+13 |
| * | target/arm: Implement SVE2 XAR | Richard Henderson | 2021-05-25 | 1 | -21/+4 |
| * | target/arm: Share unallocated_encoding() and gen_exception_insn() | Peter Maydell | 2021-05-10 | 1 | -15/+0 |
| * | target/arm: Enforce alignment for aa64 vector LDn/STn (single) | Richard Henderson | 2021-04-30 | 1 | -4/+5 |
| * | target/arm: Enforce alignment for aa64 vector LDn/STn (multiple) | Richard Henderson | 2021-04-30 | 1 | -4/+11 |
| * | target/arm: Use MemOp for size + endian in aa64 vector ld/st | Richard Henderson | 2021-04-30 | 1 | -10/+10 |
| * | target/arm: Enforce alignment for aa64 load-acq/store-rel | Richard Henderson | 2021-04-30 | 1 | -9/+14 |
| * | target/arm: Use finalize_memop for aa64 fpr load/store | Richard Henderson | 2021-04-30 | 1 | -16/+26 |
| * | target/arm: Use finalize_memop for aa64 gpr load/store | Richard Henderson | 2021-04-30 | 1 | -45/+33 |
| * | target/arm: Add ALIGN_MEM to TBFLAG_ANY | Richard Henderson | 2021-04-30 | 1 | -0/+1 |
| * | target/arm: Introduce CPUARMTBFlags | Richard Henderson | 2021-04-30 | 1 | -1/+1 |
| * | target/arm: Add wrapper macros for accessing tbflags | Richard Henderson | 2021-04-30 | 1 | -18/+18 |
| * | target/arm: Rename TBFLAG_ANY, PSTATE_SS | Richard Henderson | 2021-04-30 | 1 | -1/+1 |
| * | target/arm: Remove log2_esize parameter to gen_mte_checkN | Richard Henderson | 2021-04-30 | 1 | -8/+7 |
| * | target/arm: Merge mte_check1, mte_checkN | Richard Henderson | 2021-04-30 | 1 | -2/+2 |
| * | target/arm: Replace MTEDESC ESIZE+TSIZE with SIZEM1 | Richard Henderson | 2021-04-30 | 1 | -3/+2 |
| * | semihosting: Move include/hw/semihosting/ -> include/semihosting/ | Philippe Mathieu-Daudé | 2021-03-10 | 1 | -1/+1 |
| * | target/arm: Speed up aarch64 TBL/TBX | Richard Henderson | 2021-03-05 | 1 | -51/+7 |
| * | target/arm: Add support for FEAT_SSBS, Speculative Store Bypass Safe | Rebecca Cran | 2021-03-05 | 1 | -0/+12 |
| * | target/arm: Improve gen_top_byte_ignore | Richard Henderson | 2021-02-16 | 1 | -11/+14 |
| * | target/arm: Add support for FEAT_DIT, Data Independent Timing | Rebecca Cran | 2021-02-11 | 1 | -0/+12 |
| * | target/arm: add MMU stage 1 for Secure EL2 | Rémi Denis-Courmont | 2021-01-19 | 1 | -0/+4 |
| * | tcg: Make DisasContextBase.tb const | Richard Henderson | 2021-01-07 | 1 | -1/+1 |
| * | arm tcg cpus: Fix Lesser GPL version number | Chetan Pant | 2020-11-15 | 1 | -1/+1 |
| * | target/arm: Don't use '#' flag of printf format | Xinhao Zhang | 2020-11-10 | 1 | -2/+2 |
| * | linux-user: Set PAGE_TARGET_1 for TARGET_PROT_BTI | Richard Henderson | 2020-10-27 | 1 | -2/+2 |
| * | target/arm/translate-a64:Remove redundant statement in disas_simd_two_reg_mis... | Chen Qun | 2020-09-01 | 1 | -3/+0 |
| * | target/arm/translate-a64:Remove dead assignment in handle_scalar_simd_shli() | Chen Qun | 2020-09-01 | 1 | -2/+2 |
| * | target/arm: Convert sq{, r}dmulh to gvec for aa64 advsimd | Richard Henderson | 2020-08-28 | 1 | -10/+23 |
| * | target/arm: Convert integer multiply-add (indexed) to gvec for aa64 advsimd | Richard Henderson | 2020-08-28 | 1 | -0/+34 |
| * | target/arm: Convert integer multiply (indexed) to gvec for aa64 advsimd | Richard Henderson | 2020-08-28 | 1 | -0/+16 |
| * | target/arm: Rearrange {sve,fp}_check_access assert | Richard Henderson | 2020-08-28 | 1 | -11/+16 |
| * | target/arm: Replace A64 get_fpstatus_ptr() with generic fpstatus_ptr() | Peter Maydell | 2020-08-24 | 1 | -54/+35 |
| * | target/arm: Fix decode of LDRA[AB] instructions | Peter Collingbourne | 2020-08-04 | 1 | -2/+4 |
| * | target/arm: Avoid maybe-uninitialized warning with gcc 4.9 | Kaige Li | 2020-08-03 | 1 | -1/+1 |
| * | target/arm: Fix temp double-free in sve ldr/str | Richard Henderson | 2020-07-03 | 1 | -0/+6 |
| * | target/arm: Implement data cache set allocation tags | Richard Henderson | 2020-06-26 | 1 | -0/+39 |
| * | target/arm: Complete TBI clearing for user-only for SVE | Richard Henderson | 2020-06-26 | 1 | -0/+5 |
| * | target/arm: Handle TBI for sve scalar + int memory ops | Richard Henderson | 2020-06-26 | 1 | -1/+1 |
| * | target/arm: Add arm_tlb_bti_gp | Richard Henderson | 2020-06-26 | 1 | -1/+1 |
| * | target/arm: Add helper_mte_check_zva | Richard Henderson | 2020-06-26 | 1 | -1/+15 |
| * | target/arm: Add gen_mte_checkN | Richard Henderson | 2020-06-26 | 1 | -16/+55 |
| * | target/arm: Add gen_mte_check1 | Richard Henderson | 2020-06-26 | 1 | -24/+76 |
| * | target/arm: Implement the LDGM, STGM, STZGM instructions | Richard Henderson | 2020-06-26 | 1 | -8/+64 |
| * | target/arm: Implement the STGP instruction | Richard Henderson | 2020-06-26 | 1 | -3/+26 |
| * | target/arm: Implement LDG, STG, ST2G instructions | Richard Henderson | 2020-06-26 | 1 | -5/+167 |
| * | target/arm: Implement the SUBP instruction | Richard Henderson | 2020-06-26 | 1 | -2/+22 |
| * | target/arm: Implement the GMI instruction | Richard Henderson | 2020-06-26 | 1 | -0/+15 |
| * | target/arm: Implement the ADDG, SUBG instructions | Richard Henderson | 2020-06-26 | 1 | -0/+51 |
