| Commit message (Expand) | Author | Age | Files | Lines |
|---|
| * | exec/memop: Adding signedness to quad definitions | Frédéric Pétrot | 2022-01-08 | 1 | -5/+5 |
| * | target/arm: Use tcg_constant_i64() in do_sat_addsub_64() | Philippe Mathieu-Daudé | 2021-11-02 | 1 | -9/+8 |
| * | target/arm: Remove duplicate 'plus1' function from Neon and SVE decode | Peter Maydell | 2021-07-18 | 1 | -5/+0 |
| * | tcg: Avoid including 'trace-tcg.h' in target translate.c | Philippe Mathieu-Daudé | 2021-07-09 | 1 | -1/+0 |
| * | target/arm: Implement bfloat widening fma (indexed) | Richard Henderson | 2021-06-03 | 1 | -0/+30 |
| * | target/arm: Implement bfloat widening fma (vector) | Richard Henderson | 2021-06-03 | 1 | -0/+30 |
| * | target/arm: Implement bfloat16 matrix multiply accumulate | Richard Henderson | 2021-06-03 | 1 | -0/+12 |
| * | target/arm: Implement bfloat16 dot product (indexed) | Richard Henderson | 2021-06-03 | 1 | -0/+12 |
| * | target/arm: Implement bfloat16 dot product (vector) | Richard Henderson | 2021-06-03 | 1 | -0/+12 |
| * | target/arm: Implement vector float32 to bfloat16 conversion | Richard Henderson | 2021-06-03 | 1 | -0/+16 |
| * | target/arm: Implement integer matrix multiply accumulate | Richard Henderson | 2021-05-25 | 1 | -0/+27 |
| * | target/arm: Implement SVE2 fp multiply-add long | Stephen Long | 2021-05-25 | 1 | -0/+75 |
| * | target/arm: Implement SVE2 bitwise shift immediate | Stephen Long | 2021-05-25 | 1 | -0/+60 |
| * | target/arm: Implement 128-bit ZIP, UZP, TRN | Richard Henderson | 2021-05-25 | 1 | -0/+58 |
| * | target/arm: Implement SVE2 LD1RO | Richard Henderson | 2021-05-25 | 1 | -0/+93 |
| * | target/arm: Tidy do_ldrq | Richard Henderson | 2021-05-25 | 1 | -9/+4 |
| * | target/arm: Share table of sve load functions | Richard Henderson | 2021-05-25 | 1 | -128/+126 |
| * | target/arm: Implement SVE2 FLOGB | Stephen Long | 2021-05-25 | 1 | -0/+24 |
| * | target/arm: Implement SVE2 FCVTXNT, FCVTX | Stephen Long | 2021-05-25 | 1 | -10/+39 |
| * | target/arm: Implement SVE2 FCVTLT | Stephen Long | 2021-05-25 | 1 | -0/+16 |
| * | target/arm: Implement SVE2 FCVTNT | Richard Henderson | 2021-05-25 | 1 | -0/+16 |
| * | target/arm: Implement SVE2 TBL, TBX | Stephen Long | 2021-05-25 | 1 | -0/+33 |
| * | target/arm: Implement SVE2 crypto constructive binary operations | Richard Henderson | 2021-05-25 | 1 | -0/+16 |
| * | target/arm: Implement SVE2 crypto destructive binary operations | Richard Henderson | 2021-05-25 | 1 | -0/+38 |
| * | target/arm: Implement SVE2 crypto unary operations | Richard Henderson | 2021-05-25 | 1 | -0/+11 |
| * | target/arm: Implement SVE mixed sign dot product | Richard Henderson | 2021-05-25 | 1 | -0/+16 |
| * | target/arm: Implement SVE mixed sign dot product (indexed) | Richard Henderson | 2021-05-25 | 1 | -0/+16 |
| * | target/arm: Implement SVE2 complex integer dot product | Richard Henderson | 2021-05-25 | 1 | -0/+17 |
| * | target/arm: Implement SVE2 complex integer multiply-add (indexed) | Richard Henderson | 2021-05-25 | 1 | -0/+15 |
| * | target/arm: Implement SVE2 integer multiply long (indexed) | Richard Henderson | 2021-05-25 | 1 | -0/+10 |
| * | target/arm: Implement SVE2 multiply-add long (indexed) | Richard Henderson | 2021-05-25 | 1 | -0/+20 |
| * | target/arm: Implement SVE2 saturating multiply high (indexed) | Richard Henderson | 2021-05-25 | 1 | -0/+8 |
| * | target/arm: Implement SVE2 signed saturating doubling multiply high | Richard Henderson | 2021-05-25 | 1 | -0/+18 |
| * | target/arm: Implement SVE2 saturating multiply (indexed) | Richard Henderson | 2021-05-25 | 1 | -0/+14 |
| * | target/arm: Implement SVE2 saturating multiply-add (indexed) | Richard Henderson | 2021-05-25 | 1 | -0/+19 |
| * | target/arm: Implement SVE2 saturating multiply-add high (indexed) | Richard Henderson | 2021-05-25 | 1 | -0/+8 |
| * | target/arm: Implement SVE2 integer multiply-add (indexed) | Richard Henderson | 2021-05-25 | 1 | -0/+31 |
| * | target/arm: Implement SVE2 integer multiply (indexed) | Richard Henderson | 2021-05-25 | 1 | -0/+30 |
| * | target/arm: Split out formats for 3 vectors + 1 index | Richard Henderson | 2021-05-25 | 1 | -10/+28 |
| * | target/arm: Pass separate addend to FCMLA helpers | Richard Henderson | 2021-05-25 | 1 | -2/+3 |
| * | target/arm: Pass separate addend to {U, S}DOT helpers | Richard Henderson | 2021-05-25 | 1 | -6/+7 |
| * | target/arm: Implement SVE2 SPLICE, EXT | Stephen Long | 2021-05-25 | 1 | -5/+30 |
| * | target/arm: Implement SVE2 FMMLA | Stephen Long | 2021-05-25 | 1 | -0/+34 |
| * | target/arm: Implement SVE2 gather load insns | Stephen Long | 2021-05-25 | 1 | -0/+8 |
| * | target/arm: Implement SVE2 scatter store insns | Stephen Long | 2021-05-25 | 1 | -0/+8 |
| * | target/arm: Implement SVE2 XAR | Richard Henderson | 2021-05-25 | 1 | -0/+104 |
| * | target/arm: Implement SVE2 HISTCNT, HISTSEG | Stephen Long | 2021-05-25 | 1 | -0/+19 |
| * | target/arm: Implement SVE2 RSUBHNB, RSUBHNT | Stephen Long | 2021-05-25 | 1 | -0/+2 |
| * | target/arm: Implement SVE2 SUBHNB, SUBHNT | Stephen Long | 2021-05-25 | 1 | -0/+3 |
| * | target/arm: Implement SVE2 RADDHNB, RADDHNT | Stephen Long | 2021-05-25 | 1 | -0/+2 |
