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path: root/target/arm/translate.h
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* target/arm: Move vfp_expand_imm() to translate.[ch]Peter Maydell2019-06-171-0/+7
* target/arm: Use tcg_gen_gvec_bitselRichard Henderson2019-06-131-3/+0Star
* target/arm: Implement M-profile lazy FP state preservationPeter Maydell2019-04-291-0/+1
* target/arm: Activate M-profile floating point context when FPCCR.ASPEN is setPeter Maydell2019-04-291-0/+1
* target/arm: Set FPCCR.S when executing M-profile floating point insnsPeter Maydell2019-04-291-0/+1
* qom/cpu: Simplify how CPUClass:cpu_dump_state() printsMarkus Armbruster2019-04-181-5/+2Star
* target/arm: Add set/clear_pstate_bits, share gen_ss_advanceRichard Henderson2019-03-051-0/+34
* target/arm: Use vector operations for saturationRichard Henderson2019-02-151-0/+4
* target/arm: Add TBFLAG_A64_TBID, split out gen_top_byte_ignoreRichard Henderson2019-02-051-1/+2
* target/arm: Default handling of BTYPE during translationRichard Henderson2019-02-051-2/+7
* target/arm: Add BT and BTYPE to tb->flagsRichard Henderson2019-02-051-0/+4
* target/arm: Merge TBFLAG_AA_TB{0, 1} to TBIIRichard Henderson2019-01-211-2/+1Star
* target/arm: Add PAuth active bit to tbflagsRichard Henderson2019-01-211-0/+2
* target/arm: Use gvec for NEON_3R_VTST_VCEQ, NEON_3R_VCGT, NEON_3R_VCGERichard Henderson2018-10-241-0/+2
* target/arm: Use gvec for NEON_3R_VMLRichard Henderson2018-10-241-0/+2
* target/arm: Use gvec for VSRI, VSLIRichard Henderson2018-10-241-0/+2
* target/arm: Use gvec for VSRARichard Henderson2018-10-241-0/+2
* target/arm: Use gvec for NEON_3R_LOGIC insnsRichard Henderson2018-10-241-0/+6
* target/arm: Convert v8 extensions from feature bits to isar testsRichard Henderson2018-10-241-0/+7
* target/arm: Define new TBFLAG for v8M stack checkingPeter Maydell2018-10-081-0/+1
* target/arm: convert conversion helpers to fpst/ahp_flagAlex Bennée2018-05-181-0/+12
* target/arm: avoid integer overflow in next_page PC checkEmilio G. Cota2018-05-091-1/+1
* tcg: Introduce tcg_set_insn_start_paramRichard Henderson2018-04-101-1/+1
* target/arm: Add SVE state to TB->FLAGSRichard Henderson2018-02-091-0/+2
* target/arm: Mark disas_set_insn_syndrome inlineRichard Henderson2018-01-251-1/+1
* tcg: Dynamically allocate TCGOpsRichard Henderson2017-12-291-5/+5
* tcg: Initialize cpu_env genericallyRichard Henderson2017-10-241-1/+0Star
* Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20170907'...Peter Maydell2017-09-071-0/+1
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| * target/arm: Implement BXNS, and banked stack pointersPeter Maydell2017-09-071-0/+1
* | target/arm: [tcg] Port to generic translation frameworkLluís Vilanova2017-09-061-7/+1Star
* | target/arm: [tcg] Port to translate_insnLluís Vilanova2017-09-061-0/+1
* | target/arm: [tcg] Port to DisasContextBaseLluís Vilanova2017-09-061-5/+6
* | target: [tcg] Use a generic enum for DISAS_ valuesLluís Vilanova2017-09-061-9/+14
* | target/arm: Use DISAS_NORETURNRichard Henderson2017-09-061-6/+2Star
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* tcg: Pass generic CPUState to gen_intermediate_code()Lluís Vilanova2017-07-191-2/+2
* target/arm/translate.h: expand comment on DISAS_EXITAlex Bennée2017-07-171-1/+4
* target/arm: optimize indirect branchesEmilio G. Cota2017-06-051-0/+4
* arm: Add support for M profile CPUs having different MMU index semanticsPeter Maydell2017-06-021-1/+1
* arm: Implement M profile exception return properlyPeter Maydell2017-04-201-0/+4
* arm: Track M profile handler mode state in TB flagsPeter Maydell2017-04-201-0/+1
* target/arm: A32, T32: Create Instruction Syndromes for Data AbortsPeter Maydell2017-02-071-0/+14
* Move target-* CPU file into a target/ folderThomas Huth2016-12-201-0/+155
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