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path: root/target/arm/vfp.decode
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* target/arm: Implement VLDR/VSTR system registerPeter Maydell2020-12-101-0/+14
* arm tcg cpus: Fix Lesser GPL version numberChetan Pant2020-11-151-1/+1
* target/arm: Implement VFP fp16 VMOV between gp and halfprec registersPeter Maydell2020-09-011-0/+1
* target/arm: Implement VFP fp16 VRINT*Peter Maydell2020-09-011-0/+3
* target/arm: Implement VFP fp16 VCVT between float and fixed-pointPeter Maydell2020-09-011-0/+2
* target/arm: Implement VFP fp16 VCVT between float and integerPeter Maydell2020-09-011-0/+4
* target/arm: Implement VFP fp16 VLDR and VSTRPeter Maydell2020-09-011-2/+1Star
* target/arm: Implement VFP fp16 VCMPPeter Maydell2020-09-011-0/+2
* target/arm: Implement VFP fp16 for VMOV immediatePeter Maydell2020-09-011-0/+2
* target/arm: Implement VFP fp16 for VABS, VNEG, VSQRTPeter Maydell2020-09-011-0/+3
* target/arm: Implement VFP fp16 for fused-multiply-addPeter Maydell2020-09-011-0/+5
* target/arm: Implement VFP fp16 VMLA, VMLS, VNMLS, VNMLA, VNMULPeter Maydell2020-09-011-0/+5
* target/arm: Implement VFP fp16 for VFP_BINOP operationsPeter Maydell2020-09-011-0/+4
* target/arm: Do M-profile NOCP checks early and via decodetreePeter Maydell2020-08-241-2/+0Star
* target/arm: Split VFM decodeRichard Henderson2020-02-281-8/+9
* target/arm: Add formats for some vfp 2 and 3-register insnsRichard Henderson2020-02-281-90/+60Star
* target/arm: Move VLLDM and VLSTM to vfp.decodeRichard Henderson2020-02-281-0/+2
* target/arm: Use vfp_expand_imm() for AArch32 VFP VMOV_immPeter Maydell2019-06-171-4/+6
* target/arm: Convert float-to-integer VCVT insns to decodetreePeter Maydell2019-06-131-0/+6
* target/arm: Convert VCVT fp/fixed-point conversion insns to decodetreePeter Maydell2019-06-131-0/+10
* target/arm: Convert VJCVT to decodetreePeter Maydell2019-06-131-0/+4
* target/arm: Convert integer-to-float insns to decodetreePeter Maydell2019-06-131-0/+6
* target/arm: Convert double-single precision conversion insns to decodetreePeter Maydell2019-06-131-0/+6
* target/arm: Convert VFP round insns to decodetreePeter Maydell2019-06-131-0/+15
* target/arm: Convert the VCVT-to-f16 insns to decodetreePeter Maydell2019-06-131-0/+6
* target/arm: Convert the VCVT-from-f16 insns to decodetreePeter Maydell2019-06-131-0/+6
* target/arm: Convert VFP comparison insns to decodetreePeter Maydell2019-06-131-0/+5
* target/arm: Convert VMOV (register) to decodetreePeter Maydell2019-06-131-0/+5
* target/arm: Convert VSQRT to decodetreePeter Maydell2019-06-131-0/+5
* target/arm: Convert VNEG to decodetreePeter Maydell2019-06-131-0/+5
* target/arm: Convert VABS to decodetreePeter Maydell2019-06-131-0/+5
* target/arm: Convert VMOV (imm) to decodetreePeter Maydell2019-06-131-0/+5
* target/arm: Convert VFP fused multiply-add insns to decodetreePeter Maydell2019-06-131-0/+9
* target/arm: Convert VDIV to decodetreePeter Maydell2019-06-131-0/+5
* target/arm: Convert VSUB to decodetreePeter Maydell2019-06-131-0/+5
* target/arm: Convert VADD to decodetreePeter Maydell2019-06-131-0/+5
* target/arm: Convert VNMUL to decodetreePeter Maydell2019-06-131-0/+5
* target/arm: Convert VMUL to decodetreePeter Maydell2019-06-131-0/+5
* target/arm: Convert VFP VNMLA to decodetreePeter Maydell2019-06-131-0/+5
* target/arm: Convert VFP VNMLS to decodetreePeter Maydell2019-06-131-0/+5
* target/arm: Convert VFP VMLS to decodetreePeter Maydell2019-06-131-0/+5
* target/arm: Convert VFP VMLA to decodetreePeter Maydell2019-06-131-0/+6
* target/arm: Convert the VFP load/store multiple insns to decodetreePeter Maydell2019-06-131-0/+18
* target/arm: Convert VFP VLDR and VSTR to decodetreePeter Maydell2019-06-131-0/+7
* target/arm: Convert VFP two-register transfer insns to decodetreePeter Maydell2019-06-131-0/+5
* target/arm: Convert "single-precision" register moves to decodetreePeter Maydell2019-06-131-0/+4
* target/arm: Convert "double-precision" register moves to decodetreePeter Maydell2019-06-131-0/+36
* target/arm: Add stubs for AArch32 VFP decodetreePeter Maydell2019-06-131-0/+28