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* cpu: refactor cpu_address_space_init()Peter Xu2017-12-211-10/+3Star
* target/arm: Extend PAR format determinationEdgar E. Iglesias2017-12-131-4/+29
* target/arm: Remove fsr argument from get_phys_addr() and arm_tlb_fill()Peter Maydell2017-12-133-34/+16Star
* target/arm: Ignore fsr from get_phys_addr() in do_ats_write()Peter Maydell2017-12-131-6/+10
* target/arm: Use ARMMMUFaultInfo in deliver_fault()Peter Maydell2017-12-131-57/+22Star
* target/arm: Convert get_phys_addr_pmsav8() to not return FSC valuesPeter Maydell2017-12-131-11/+18
* target/arm: Convert get_phys_addr_pmsav7() to not return FSC valuesPeter Maydell2017-12-131-4/+7
* target/arm: Convert get_phys_addr_pmsav5() to not return FSC valuesPeter Maydell2017-12-131-7/+13
* target/arm: Convert get_phys_addr_lpae() to not return FSC valuesPeter Maydell2017-12-131-23/+18Star
* target/arm: Convert get_phys_addr_v6() to not return FSC valuesPeter Maydell2017-12-131-18/+22
* target/arm: Convert get_phys_addr_v5() to not return FSC valuesPeter Maydell2017-12-131-15/+18
* target/arm: Remove fsr argument from arm_ld*_ptw()Peter Maydell2017-12-131-13/+11Star
* target/arm: Provide fault type enum and FSR conversion functionsPeter Maydell2017-12-131-0/+185
* target/arm: Implement TT instructionPeter Maydell2017-12-133-1/+138
* target/arm: Factor MPU lookup code out of get_phys_addr_pmsav8()Peter Maydell2017-12-131-51/+79
* target/arm: Create new arm_v7m_mmu_idx_for_secstate_and_priv()Peter Maydell2017-12-131-5/+16
* target/arm: Split M profile MNegPri mmu index into user and privPeter Maydell2017-12-134-29/+50
* target/arm: Add missing M profile case to regime_is_user()Peter Maydell2017-12-131-0/+1
* target/arm: Allow explicit writes to CONTROL.SPSEL in Handler modePeter Maydell2017-12-131-1/+4
* target/arm: Handle SPSEL and current stack being out of sync in MSP/PSP readsPeter Maydell2017-12-131-6/+4Star
* target/arm: Generate UNDEF for 32-bit Thumb2 insnsPeter Maydell2017-12-111-1/+4
* arm: check regime, not current state, for ATS write PAR formatPeter Maydell2017-11-201-1/+1
* target/arm: Report GICv3 sysregs present in ID registers if neededPeter Maydell2017-11-201-4/+40
* target/arm: Fix GETPC usage in do_paired_cmpxchg64_l/beRichard Henderson2017-11-151-8/+6Star
* target/arm: Use helper_retaddr in stxp helpersRichard Henderson2017-11-151-0/+6
* arm/translate-a64: mark path as unreachable to eliminate warningEmilio G. Cota2017-11-131-0/+2
* disas: Dump insn bytes along with capstone disassemblyRichard Henderson2017-11-091-0/+6
* translate.c: Fix usermode big-endian AArch32 LDREXD and STREXDPeter Maydell2017-11-071-5/+34
* arm: implement cache/shareability attribute bits for PAR registersAndrew Baumann2017-11-071-14/+164
* fix WFI/WFE length in syndrome registerStefano Stabellini2017-10-316-8/+23
* Merge remote-tracking branch 'remotes/rth/tags/pull-dis-20171026' into stagingPeter Maydell2017-10-273-28/+27Star
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| * arm: Support Capstone in disas_set_infoRichard Henderson2017-10-251-3/+18
| * disas: Remove unused flags argumentsRichard Henderson2017-10-252-4/+2Star
| * target/arm: Don't set INSN_ARM_BE32 for CONFIG_USER_ONLYRichard Henderson2017-10-251-2/+7
| * target/arm: Move BE32 disassembler fixupRichard Henderson2017-10-251-19/+0Star
* | tcg: Avoid setting tcg_initialize if !CONFIG_TCGRichard Henderson2017-10-261-0/+2
* | tcg: Initialize cpu_env genericallyRichard Henderson2017-10-242-5/+0Star
* | tcg: define tcg_init_ctx and make tcg_ctx a pointerEmilio G. Cota2017-10-241-1/+1
* | target/arm: check CF_PARALLEL instead of parallel_cpusEmilio G. Cota2017-10-245-21/+68
* | tcg: convert tb->cflags reads to tb_cflags(tb)Emilio G. Cota2017-10-242-6/+7
* | qom: Introduce CPUClass.tcg_initializeRichard Henderson2017-10-241-5/+1Star
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* target/arm: Implement SG instruction corner casesPeter Maydell2017-10-121-1/+22
* target/arm: Support some Thumb insns being always unconditionalPeter Maydell2017-10-121-1/+47
* target-arm: Simplify insn_crosses_page()Peter Maydell2017-10-121-21/+6Star
* target/arm: Pull Thumb insn word loads up to top levelPeter Maydell2017-10-121-70/+108
* target-arm: Don't check for "Thumb2 or M profile" for not-Thumb1Peter Maydell2017-10-121-2/+1Star
* target/arm: Implement secure function returnPeter Maydell2017-10-123-10/+126
* target/arm: Implement BLXNSPeter Maydell2017-10-124-2/+76
* target/arm: Implement SG instructionPeter Maydell2017-10-121-5/+127
* target/arm: Add M profile secure MMU index values to get_a32_user_mem_index()Peter Maydell2017-10-121-0/+4
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