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* target/arm: Implement SVE Predicate Logical Operations GroupRichard Henderson2018-05-185-1/+429
* target/arm: Implement SVE predicate testRichard Henderson2018-05-186-1/+171
* target/arm: Implement SVE load vector/predicateRichard Henderson2018-05-182-0/+147
* target/arm: Implement SVE Bitwise Logical - Unpredicated GroupRichard Henderson2018-05-181-8/+47
* target/arm: Add SVE decode skeletonRichard Henderson2018-05-184-1/+124
* target/arm: Introduce translate-a64.hRichard Henderson2018-05-182-97/+133
* target/arm: Add the XML dynamic generationAbdallah Bouassida2018-05-184-0/+129
* target/arm: Add "_S" suffix to the secure version of a sysregAbdallah Bouassida2018-05-181-11/+18
* target/arm: Add "ARM_CP_NO_GDB" as a new bit field for ARMCPRegInfo typeAbdallah Bouassida2018-05-182-2/+3
* target/arm: Remove floatX_maybe_silence_nan from conversionsRichard Henderson2018-05-182-11/+2Star
* target/arm: Use floatX_silence_nan when we have already checked for SNaNRichard Henderson2018-05-182-9/+9
* target/arm: squash FZ16 behaviour for conversionsAlex Bennée2018-05-181-4/+36
* target/arm: convert conversion helpers to fpst/ahp_flagAlex Bennée2018-05-185-77/+112
* target/arm: Fix sqrt_f16 exception raisingAlex Bennée2018-05-151-1/+2
* target/arm: Implement FMOV (immediate) for fp16Alex Bennée2018-05-151-3/+17
* target/arm: Implement FCSEL for fp16Alex Bennée2018-05-151-6/+25
* target/arm: Implement FCMP for fp16Alex Bennée2018-05-153-17/+83
* target/arm: Implement FP data-processing (3 source) for fp16Richard Henderson2018-05-151-0/+48
* target/arm: Implement FP data-processing (2 source) for fp16Richard Henderson2018-05-151-0/+65
* target/arm: Introduce and use read_fp_hregRichard Henderson2018-05-151-16/+14Star
* target/arm: Implement FCVT (scalar, fixed-point) for fp16Richard Henderson2018-05-151-2/+15
* target/arm: Implement FCVT (scalar, integer) for fp16Richard Henderson2018-05-153-18/+122
* target/arm: Early exit after unallocated_encoding in disas_fp_int_convRichard Henderson2018-05-151-1/+1
* target/arm: Implement FMOV (general) for fp16Richard Henderson2018-05-151-0/+21
* target/arm: Fix fp_status_f16 tininess before roundingPeter Maydell2018-05-151-0/+2
* Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20180510'...Peter Maydell2018-05-117-122/+464
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| * target/arm: Clear SVE high bits for FMOVRichard Henderson2018-05-101-12/+5Star
| * target/arm: Fix float16 to/from int16Richard Henderson2018-05-103-6/+55
| * target/arm: Implement vector shifted FCVT for fp16Richard Henderson2018-05-101-18/+45
| * target/arm: Implement vector shifted SCVF/UCVF for fp16Richard Henderson2018-05-101-13/+20
| * target/arm: Enable ARM_FEATURE_V8_ATOMICS for user-onlyRichard Henderson2018-05-101-0/+1
| * target/arm: Implement CAS and CASPRichard Henderson2018-05-103-3/+161
| * target/arm: Fill in disas_ldst_atomicRichard Henderson2018-05-101-2/+36
| * target/arm: Introduce ARM_FEATURE_V8_ATOMICS and initial decodeRichard Henderson2018-05-102-43/+134
| * target/arm: Use new min/max expandersRichard Henderson2018-05-101-32/+14Star
* | translator: merge max_insns into DisasContextBaseEmilio G. Cota2018-05-092-11/+6Star
* | target/arm: avoid integer overflow in next_page PC checkEmilio G. Cota2018-05-092-7/+6Star
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* target/arm/kvm: Translate the MSI doorbell in kvm_arch_fixup_msi_routeEric Auger2018-05-042-1/+40
* target/arm: Implement v8M VLLDM and VLSTMPeter Maydell2018-05-041-1/+16
* target/arm: Tidy condition in disas_simd_two_reg_miscRichard Henderson2018-05-041-1/+5
* target/arm: Tidy conditions in handle_vec_simd_shriRichard Henderson2018-05-041-5/+1Star
* target/arm: Correct MPUIR privilege level in register_cp_regs_for_features() ...Mathew Maidment2018-05-041-1/+1
* target/arm: Make PMOVSCLR and PMUSERENR 64 bits wideAaron Lindsay2018-04-262-4/+5
* target/arm: Fix bitmask for PMCCFILTR writesAaron Lindsay2018-04-261-1/+1
* target/arm: Allow EL change hooks to do IOAaron Lindsay2018-04-262-0/+18
* target/arm: Add pre-EL change hooksAaron Lindsay2018-04-265-9/+58
* target/arm: Support multiple EL change hooksAaron Lindsay2018-04-263-18/+30
* target/arm: Fetch GICv3 state directly from CPUARMStateAaron Lindsay2018-04-261-10/+0Star
* target/arm: Mask PMU register writes based on PMCR_EL0.NAaron Lindsay2018-04-261-9/+22
* target/arm: Treat PMCCNTR as alias of PMCCNTR_EL0Aaron Lindsay2018-04-261-1/+1