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path: root/target/avr/translate.c
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* target/avr: Drop checks for singlestep_enabledRichard Henderson2021-10-161-15/+4Star
* target/avr: Fix compiler errors (-Werror=enum-conversion)Stefan Weil2021-09-161-5/+3Star
* accel/tcg: Remove TranslatorOps.breakpoint_checkRichard Henderson2021-07-211-18/+0Star
* target/avr: Implement gdb_adjust_breakpointRichard Henderson2021-07-211-14/+0Star
* target/avr: Use translator_use_goto_tbRichard Henderson2021-07-091-3/+6
* target/avr: Convert to TranslatorOpsRichard Henderson2021-06-291-104/+126
* target/avr: Change ctx to DisasContext* in gen_intermediate_codeRichard Henderson2021-06-291-41/+43
* target/avr: Add DisasContextBase to DisasContextRichard Henderson2021-06-291-29/+29
* meson: targetPaolo Bonzini2020-08-211-1/+1
* meson: rename included C source files to .c.incPaolo Bonzini2020-08-211-1/+1
* target/avr: Add support for disassembling via option '-d in_asm'Michael Rolnik2020-07-111-0/+12
* target/avr: Initialize TCG register variablesMichael Rolnik2020-07-111-0/+29
* target/avr: Add instruction translation - CPU main translation functionMichael Rolnik2020-07-111-0/+213
* target/avr: Add instruction translation - MCU Control InstructionsMichael Rolnik2020-07-111-0/+65
* target/avr: Add instruction translation - Bit and Bit-test InstructionsMichael Rolnik2020-07-111-0/+247
* target/avr: Add instruction translation - Data Transfer InstructionsMichael Rolnik2020-07-111-0/+990
* target/avr: Add instruction translation - Branch InstructionsMichael Rolnik2020-07-111-0/+543
* target/avr: Add instruction translation - Arithmetic and Logic InstructionsMichael Rolnik2020-07-111-0/+820
* target/avr: Add instruction translation - Register definitionsMichael Rolnik2020-07-111-0/+142
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