summaryrefslogtreecommitdiffstats
path: root/target/hexagon
Commit message (Collapse)AuthorAgeFilesLines
* exec/exec-all: Move 'qemu/log.h' include in units requiring itPhilippe Mathieu-Daudé2022-02-212-0/+3
| | | | | | | | | | | | | Many files use "qemu/log.h" declarations but neglect to include it (they inherit it via "exec/exec-all.h"). "exec/exec-all.h" is a core component and shouldn't be used that way. Move the "qemu/log.h" inclusion locally to each unit requiring it. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Acked-by: Thomas Huth <thuth@redhat.com> Message-Id: <20220207082756.82600-10-f4bug@amsat.org> Signed-off-by: Thomas Huth <thuth@redhat.com>
* target/hexagon/cpu.h: don't include qemu-common.hPeter Maydell2021-12-151-1/+0Star
| | | | | | | | | | | | | | | The qemu-common.h header is not supposed to be included from any other header files, only from .c files (as documented in a comment at the start of it). Move the include to linux-user/hexagon/cpu_loop.c, which needs it for the declaration of cpu_exec_step_atomic(). Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Taylor Simpson <tsimpson@quicinc.com> Message-id: 20211129200510.1233037-3-peter.maydell@linaro.org
* Merge remote-tracking branch 'remotes/quic/tags/pull-hex-20211103' into stagingRichard Henderson2021-11-0438-47/+7557
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This series adds support for the Hexagon Vector eXtensions (HVX) These instructions are documented here https://developer.qualcomm.com/downloads/qualcomm-hexagon-v66-hvx-programmer-s-reference-manual Hexagon HVX is a wide vector engine with 128 byte vectors. See patch 01 Hexagon HVX README for more information. *** Changes in v2 *** Remove HVX tests from makefile to avoid need for toolchain upgrade # gpg: Signature made Wed 03 Nov 2021 05:14:44 PM EDT # gpg: using RSA key 7B0244FB12DE4422 # gpg: Good signature from "Taylor Simpson (Rock on) <tsimpson@quicinc.com>" [marginal] # gpg: WARNING: This key is not certified with sufficiently trusted signatures! # gpg: It is not certain that the signature belongs to the owner. # Primary key fingerprint: 3635 C788 CE62 B91F D4C5 9AB4 7B02 44FB 12DE 4422 * remotes/quic/tags/pull-hex-20211103: (30 commits) Hexagon HVX (tests/tcg/hexagon) histogram test Hexagon HVX (tests/tcg/hexagon) scatter_gather test Hexagon HVX (tests/tcg/hexagon) hvx_misc test Hexagon HVX (tests/tcg/hexagon) vector_add_int test Hexagon HVX (target/hexagon) import instruction encodings Hexagon HVX (target/hexagon) instruction decoding Hexagon HVX (target/hexagon) import semantics Hexagon HVX (target/hexagon) helper overrides - vector stores Hexagon HVX (target/hexagon) helper overrides - vector loads Hexagon HVX (target/hexagon) helper overrides - vector splat and abs Hexagon HVX (target/hexagon) helper overrides - vector compares Hexagon HVX (target/hexagon) helper overrides - vector logical ops Hexagon HVX (target/hexagon) helper overrides - vector max/min Hexagon HVX (target/hexagon) helper overrides - vector shifts Hexagon HVX (target/hexagon) helper overrides - vector add & sub Hexagon HVX (target/hexagon) helper overrides - vector assign & cmov Hexagon HVX (target/hexagon) helper overrides for histogram instructions Hexagon HVX (target/hexagon) helper overrides infrastructure Hexagon HVX (target/hexagon) TCG generation Hexagon HVX (target/hexagon) helper functions ... Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
| * Hexagon HVX (target/hexagon) import instruction encodingsTaylor Simpson2021-11-034-0/+819
| | | | | | | | | | Acked-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Taylor Simpson <tsimpson@quicinc.com>
| * Hexagon HVX (target/hexagon) instruction decodingTaylor Simpson2021-11-034-2/+283
| | | | | | | | | | | | | | Add new file to target/hexagon/meson.build Acked-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Taylor Simpson <tsimpson@quicinc.com>
| * Hexagon HVX (target/hexagon) import semanticsTaylor Simpson2021-11-034-0/+2804
| | | | | | | | | | | | | | | | | | | | | | Imported from the Hexagon architecture library imported/allext.idef Top level file for all extensions imported/mmvec/ext.idef HVX instruction definitions Support functions added to target/hexagon/genptr.c Acked-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Taylor Simpson <tsimpson@quicinc.com>
| * Hexagon HVX (target/hexagon) helper overrides - vector storesTaylor Simpson2021-11-031-0/+218
| | | | | | | | | | Acked-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Taylor Simpson <tsimpson@quicinc.com>
| * Hexagon HVX (target/hexagon) helper overrides - vector loadsTaylor Simpson2021-11-031-0/+150
| | | | | | | | | | Acked-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Taylor Simpson <tsimpson@quicinc.com>
| * Hexagon HVX (target/hexagon) helper overrides - vector splat and absTaylor Simpson2021-11-031-0/+26
| | | | | | | | | | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Taylor Simpson <tsimpson@quicinc.com>
| * Hexagon HVX (target/hexagon) helper overrides - vector comparesTaylor Simpson2021-11-031-0/+103
| | | | | | | | | | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Taylor Simpson <tsimpson@quicinc.com>
| * Hexagon HVX (target/hexagon) helper overrides - vector logical opsTaylor Simpson2021-11-031-0/+42
| | | | | | | | | | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Taylor Simpson <tsimpson@quicinc.com>
| * Hexagon HVX (target/hexagon) helper overrides - vector max/minTaylor Simpson2021-11-031-0/+34
| | | | | | | | | | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Taylor Simpson <tsimpson@quicinc.com>
| * Hexagon HVX (target/hexagon) helper overrides - vector shiftsTaylor Simpson2021-11-031-0/+122
| | | | | | | | | | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Taylor Simpson <tsimpson@quicinc.com>
| * Hexagon HVX (target/hexagon) helper overrides - vector add & subTaylor Simpson2021-11-031-0/+50
| | | | | | | | | | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Taylor Simpson <tsimpson@quicinc.com>
| * Hexagon HVX (target/hexagon) helper overrides - vector assign & cmovTaylor Simpson2021-11-031-0/+31
| | | | | | | | | | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Taylor Simpson <tsimpson@quicinc.com>
| * Hexagon HVX (target/hexagon) helper overrides for histogram instructionsTaylor Simpson2021-11-031-0/+106
| | | | | | | | | | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Taylor Simpson <tsimpson@quicinc.com>
| * Hexagon HVX (target/hexagon) helper overrides infrastructureTaylor Simpson2021-11-036-9/+35
| | | | | | | | | | | | | | | | | | | | Build the infrastructure to create overrides for HVX instructions. We create a new empty file (gen_tcg_hvx.h) that will be populated in subsequent patches. Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Taylor Simpson <tsimpson@quicinc.com>
| * Hexagon HVX (target/hexagon) TCG generationTaylor Simpson2021-11-033-4/+311
| | | | | | | | | | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Taylor Simpson <tsimpson@quicinc.com>
| * Hexagon HVX (target/hexagon) helper functionsTaylor Simpson2021-11-032-2/+296
| | | | | | | | | | | | | | | | | | | | Probe and commit vector stores (masked and scatter/gather) Log vector register writes Add the execution counters to the debug log Histogram instructions Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Taylor Simpson <tsimpson@quicinc.com>
| * Hexagon HVX (target/hexagon) instruction utility functionsTaylor Simpson2021-11-033-0/+73
| | | | | | | | | | | | | | | | Functions to support scatter/gather Add new file to target/hexagon/meson.build Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Taylor Simpson <tsimpson@quicinc.com>
| * Hexagon HVX (target/hexagon) C preprocessor for decode treeTaylor Simpson2021-11-031-0/+13
| | | | | | | | | | Acked-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Taylor Simpson <tsimpson@quicinc.com>
| * Hexagon HVX (target/hexagon) semantics generator - part 2Taylor Simpson2021-11-033-22/+360
| | | | | | | | | | Acked-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Taylor Simpson <tsimpson@quicinc.com>
| * Hexagon HVX (target/hexagon) semantics generatorTaylor Simpson2021-11-032-0/+46
| | | | | | | | | | | | | | Add HVX support to the semantics generator Acked-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Taylor Simpson <tsimpson@quicinc.com>
| * Hexagon HVX (target/hexagon) import macro definitionsTaylor Simpson2021-11-033-0/+955
| | | | | | | | | | | | | | | | | | | | | | | | Imported from the Hexagon architecture library imported/allext_macros.def Top level macro include for all extensions imported/macros.def Scalar core macros (some HVX here) imported/mmvec/macros.def HVX macro definitions The macro definition files specify instruction attributes that are applied to each instruction that reverences the macro. Acked-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Taylor Simpson <tsimpson@quicinc.com>
| * Hexagon HVX (target/hexagon) macrosTaylor Simpson2021-11-032-0/+376
| | | | | | | | | | | | | | | | macros to interface with the generator macros referenced in instruction semantics Acked-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Taylor Simpson <tsimpson@quicinc.com>
| * Hexagon HVX (target/hexagon) instruction attributesTaylor Simpson2021-11-031-0/+22
| | | | | | | | | | Acked-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Taylor Simpson <tsimpson@quicinc.com>
| * Hexagon HVX (target/hexagon) register namesTaylor Simpson2021-11-032-1/+2
| | | | | | | | | | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Taylor Simpson <tsimpson@quicinc.com>
| * Hexagon HVX (target/hexagon) add Hexagon Vector eXtensions (HVX) to coreTaylor Simpson2021-11-036-6/+200
| | | | | | | | | | | | | | | | | | | | | | HVX is a set of wide vector instructions. Machine state includes vector registers (VRegs) vector predicate registers (QRegs) temporary registers for intermediate values store buffer (masked stores and scatter/gather) Acked-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Taylor Simpson <tsimpson@quicinc.com>
| * Hexagon HVX (target/hexagon) READMETaylor Simpson2021-11-031-1/+80
| | | | | | | | | | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Taylor Simpson <tsimpson@quicinc.com>
* | target/hexagon: Remove hexagon_cpu_tlb_fillRichard Henderson2021-11-021-23/+0Star
|/ | | | | | | | | | The fallback code in cpu_loop_exit_sigsegv is sufficient for hexagon linux-user. Remove the code from cpu_loop that raises SIGSEGV. Reviewed-by: Taylor Simpson <tsimpson@quicinc.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* Hexagon (target/hexagon) put writes to USR into temp until commitTaylor Simpson2021-10-294-2/+12
| | | | | | | | | | | | | | | Change SET_USR_FIELD to write to hex_new_value[HEX_REG_USR] instead of hex_gpr[HEX_REG_USR]. Then, we need code to mark the instructions that can set implicitly set USR - Macros added to hex_common.py - A_FPOP added in translate.c Test case added in tests/tcg/hexagon/overflow.c Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Taylor Simpson <tsimpson@quicinc.com>
* Hexagon (target/hexagon) more tcg_constant_*Taylor Simpson2021-10-294-21/+9Star
| | | | | | | | | | | | | | Change additional tcg_const_tl to tcg_constant_tl Note that gen_pred_cancal had slot_mask initialized with tcg_const_tl. However, it is not constant throughout, so we initialize it with tcg_temp_new and replace the first use with the constant value. Inspired-by: Richard Henderson <richard.henderson@linaro.org> Inspired-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Taylor Simpson <tsimpson@quicinc.com>
* target/hexagon: Drop checks for singlestep_enabledRichard Henderson2021-10-161-10/+2Star
| | | | | | | GDB single-stepping is now handled generically. Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* target/hexagon: Implement cpu_mmu_indexRichard Henderson2021-10-131-0/+9
| | | | | | | | The function is trivial for user-only, but still must be present. Reviewed-by: Taylor Simpson <tsimpson@quicinc.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* target/hexagon: Use tcg_constant_*Philippe Mathieu-Daudé2021-10-065-53/+25Star
| | | | | | | | | | Replace uses of tcg_const_* with the allocate and free close together. Inspired-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Taylor Simpson <tsimpson@quicinc.com> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20211003004750.3608983-3-f4bug@amsat.org>
* target/hexagon: Remove unused TCG temporary from predicated loadsPhilippe Mathieu-Daudé2021-10-061-2/+0Star
| | | | | | | | | | The gen_pred_cancel() function, introduced in commit a646e99cb90 (Hexagon macros) doesn't use the 'one' TCG temporary; remove it. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Taylor Simpson <tsimpson@quicinc.com> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20211003004750.3608983-2-f4bug@amsat.org>
* Hexagon (target/hexagon) probe the stores in a packet at start of commitTaylor Simpson2021-10-063-3/+53
| | | | | | | | | | | | | | | | | | | When a packet has 2 stores, either both commit or neither commit. At the beginning of gen_commit_packet, we check for multiple stores. If there are multiple stores, call a helper that will probe each of them before proceeding with the commit. Note that we don't call the probe helper for packets with only one store. Therefore, we call process_store_log before anything else involved in committing the packet. We also fix a typo in the comment in process_store_log. Test case added in tests/tcg/hexagon/hex_sigsegv.c Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Taylor Simpson <tsimpson@quicinc.com> Message-Id: <1633036599-7637-1-git-send-email-tsimpson@quicinc.com>
* hexagon: use env keyword argument to pass PYTHONPATHPaolo Bonzini2021-10-051-1/+2
| | | | | | This feature is new in meson 0.57 and allows getting rid of the "env" wrapper. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
* include/exec: Move cpu_signal_handler declarationRichard Henderson2021-09-221-3/+0Star
| | | | | | | | | | There is nothing target specific about this. The implementation is host specific, but the declaration is 100% common. Reviewed-By: Warner Losh <imp@bsdimp.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* accel/tcg: Add DisasContextBase argument to translator_ld*Ilya Leoshkevich2021-09-141-1/+2
| | | | | | Signed-off-by: Ilya Leoshkevich <iii@linux.ibm.com> [rth: Split out of a larger patch.] Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* Merge remote-tracking branch 'remotes/quic/tags/pull-hex-20210725' into stagingPeter Maydell2021-07-261-22/+20Star
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The Hexagon target was silently failing the SIGSEGV test because the signal handler was not called. Patch 1/2 fixes the Hexagon target Patch 2/2 drops include qemu.h from target/hexagon/op_helper.c **** Changes in v2 **** Drop changes to linux-test.c due to intermittent failures on riscv # gpg: Signature made Sun 25 Jul 2021 22:39:38 BST # gpg: using RSA key 7B0244FB12DE4422 # gpg: Good signature from "Taylor Simpson (Rock on) <tsimpson@quicinc.com>" [undefined] # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: 3635 C788 CE62 B91F D4C5 9AB4 7B02 44FB 12DE 4422 * remotes/quic/tags/pull-hex-20210725: target/hexagon: Drop include of qemu.h Hexagon (target/hexagon) remove put_user_*/get_user_* Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * target/hexagon: Drop include of qemu.hPeter Maydell2021-07-211-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The qemu.h file is a CONFIG_USER_ONLY header; it doesn't appear on the include path for softmmu builds. Currently we include it unconditionally in target/hexagon/op_helper.c. We used to need it for the put_user_*() and get_user_*() functions, but now that we have removed the uses of those from op_helper.c, the only reason it's still there is that we're implicitly relying on it pulling in some other headers. Explicitly include the headers we need for other functions, and drop the include of qemu.h. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-Id: <20210717103017.20491-1-peter.maydell@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Taylor Simpson <tsimpson@quicinc.com> Signed-off-by: Taylor Simpson <tsimpson@quicinc.com>
| * Hexagon (target/hexagon) remove put_user_*/get_user_*Taylor Simpson2021-07-211-21/+18Star
| | | | | | | | | | | | | | | | | | | | Replace put_user_* with cpu_st*_data_ra Replace get_user_* with cpu_ld*_data_ra Suggested-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Taylor Simpson <tsimpson@quicinc.com> Message-Id: <1626384156-6248-2-git-send-email-tsimpson@quicinc.com>
* | accel/tcg: Remove TranslatorOps.breakpoint_checkRichard Henderson2021-07-211-17/+0Star
|/ | | | | | | | | The hook is now unused, with breakpoints checked outside translation. Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* Hexagon (target/hexagon) remove unused TCG variablesTaylor Simpson2021-06-292-15/+2Star
| | | | | | Signed-off-by: Taylor Simpson <tsimpson@quicinc.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <1622589584-22571-5-git-send-email-tsimpson@quicinc.com>
* Hexagon (target/hexagon) cleanup gen_store_conditional[48] functionsTaylor Simpson2021-06-293-16/+7Star
| | | | | | | | | | | | | | | Previously the store-conditional code was writing to hex_pred[prednum]. Then, the fGEN_TCG override was reading from there to the destination variable so that the packet commit logic would handle it properly. The correct implementation is to write to the destination variable and don't have the extra read in the override. Remove the unused arguments from gen_store_conditional[48] Signed-off-by: Taylor Simpson <tsimpson@quicinc.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <1622589584-22571-4-git-send-email-tsimpson@quicinc.com>
* Hexagon (target/hexagon) fix l2fetch instructionsTaylor Simpson2021-06-292-0/+14
| | | | | | | | | | | | | | | | Y4_l2fetch == l2fetch(Rs32, Rt32) Y5_l2fetch == l2fetch(Rs32, Rtt32) The semantics for these instructions are present, but the encodings are missing. Note that these are treated as nops in qemu, so we add overrides. Test case added to tests/tcg/hexagon/misc.c Signed-off-by: Taylor Simpson <tsimpson@quicinc.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <1622589584-22571-3-git-send-email-tsimpson@quicinc.com>
* Hexagon (target/hexagon) fix bug in fLSBNEW*Taylor Simpson2021-06-292-22/+10Star
| | | | | | | | | | | | Change fLSBNEW/fLSBNEW0/fLSBNEW1 from copy to "x & 1" Remove gen_logical_not function Clean up fLSBNEWNOT to use andi-1 followed by xori-1 Test cases added to tests/tcg/hexagon/misc.c Signed-off-by: Taylor Simpson <tsimpson@quicinc.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <1622589584-22571-2-git-send-email-tsimpson@quicinc.com>
* hw/core: Constify TCGCPUOpsRichard Henderson2021-05-271-1/+1
| | | | | | | | | | We no longer have any runtime modifications to this struct, so declare them all const. Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-ID: <20210227232519.222663-3-richard.henderson@linaro.org>
* Merge remote-tracking branch ↵Peter Maydell2021-05-053-3/+0Star
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | 'remotes/vivier2/tags/trivial-branch-for-6.1-pull-request' into staging Trivial patches pull request 20210503 # gpg: Signature made Mon 03 May 2021 09:34:56 BST # gpg: using RSA key CD2F75DDC8E3A4DC2E4F5173F30C38BD3F2FBE3C # gpg: issuer "laurent@vivier.eu" # gpg: Good signature from "Laurent Vivier <lvivier@redhat.com>" [full] # gpg: aka "Laurent Vivier <laurent@vivier.eu>" [full] # gpg: aka "Laurent Vivier (Red Hat) <lvivier@redhat.com>" [full] # Primary key fingerprint: CD2F 75DD C8E3 A4DC 2E4F 5173 F30C 38BD 3F2F BE3C * remotes/vivier2/tags/trivial-branch-for-6.1-pull-request: (23 commits) hw/rx/rx-gdbsim: Do not accept invalid memory size docs: More precisely describe memory-backend-*::id's user scripts: fix generation update-binfmts templates docs/system: Document the removal of "compat" property for POWER CPUs mc146818rtc: put it into the 'misc' category Do not include exec/address-spaces.h if it's not really necessary Do not include cpu.h if it's not really necessary Do not include hw/boards.h if it's not really necessary Do not include sysemu/sysemu.h if it's not really necessary hw: Do not include qemu/log.h if it is not necessary hw: Do not include hw/irq.h if it is not necessary hw: Do not include hw/sysbus.h if it is not necessary hw: Remove superfluous includes of hw/hw.h ui: Fix memory leak in qemu_xkeymap_mapping_table() hw/usb: Constify VMStateDescription hw/display/qxl: Constify VMStateDescription hw/arm: Constify VMStateDescription vmstate: Constify some VMStateDescriptions Fix typo in CFI build documentation hw/pcmcia: Do not register PCMCIA type if not required ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
generated by cgit v1.2.3-55-g7522 (git 2.39.0) at 2024-12-12 03:52:49 +0100