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* target/hexagon: Convert to tcg_ops restore_state_to_opcRichard Henderson2022-10-261-2/+7
| | | | | Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* Merge tag 'pull-hex-20221003' of https://github.com/quic/qemu into stagingStefan Hajnoczi2022-10-059-137/+192
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Make store handling faster and more robust Bug fix in gen_tcg_funcs.py # -----BEGIN PGP SIGNATURE----- # # iQEzBAABCgAdFiEENjXHiM5iuR/UxZq0ewJE+xLeRCIFAmM7JS4ACgkQewJE+xLe # RCJXxQf9ESfI6LVoB1VBsMs69WOHqhy1HUEVzM4Ku+CgDCNaFRRz7xFoy/sv4FOX # D7h5aYVuCLrX/KfttV6V+1GXX/XIyjMN81uZZ8/eiCvjt7D/9fkrUxp9E1Gh6KlV # Dci21OYjh4aStd4tXin0vPHN5wG+IuuYuSzj0Xvu8SzRjFYKsFkjfxPrVsm1zWvN # G1FfiUJ6AveRf9SJVuMTmLHY7jo9hg0/tpm7YpnxlIgzDVZbZDa1yDwaLEg/m6AT # GFHli/nOEsL1c6mbYmvVnGoSupjEj0+MfNIeOUrn8D5Gd66OgvU+FVVFBJQ4ZKi6 # ZuckxBjBE3d5XKyxCVryRA3at+WLYA== # =ron6 # -----END PGP SIGNATURE----- # gpg: Signature made Mon 03 Oct 2022 14:08:46 EDT # gpg: using RSA key 3635C788CE62B91FD4C59AB47B0244FB12DE4422 # gpg: Good signature from "Taylor Simpson (Rock on) <tsimpson@quicinc.com>" [unknown] # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: 3635 C788 CE62 B91F D4C5 9AB4 7B02 44FB 12DE 4422 * tag 'pull-hex-20221003' of https://github.com/quic/qemu: Hexagon (gen_tcg_funcs.py): avoid duplicated tcg code on A_CVI_NEW Hexagon (target/hexagon) move store size tracking to translation Hexagon (target/hexagon) Change decision to set pkt_has_store_s[01] Hexagon (target/hexagon) add instruction attributes from archlib Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
| * Hexagon (gen_tcg_funcs.py): avoid duplicated tcg code on A_CVI_NEWMatheus Tavares Bernardino2022-10-031-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Hexagon instructions with the A_CVI_NEW attribute produce a vector value that can be used in the same packet. The python function responsible for generating code for such instructions has a typo ("if" instead of "elif"), which makes genptr_dst_write_ext() be executed twice, thus also generating the same tcg code twice. Fortunately, this doesn't cause any problems for correctness, but it is less efficient than it could be. Fix it by using an "elif" and avoiding the unnecessary extra code gen. Signed-off-by: Matheus Tavares Bernardino <quic_mathbern@quicinc.com> Signed-off-by: Taylor Simpson <tsimpson@quicinc.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Taylor Simpson <tsimpson@quicinc.com> Message-Id: <fa706b192b2a3a0ffbd399fa8dbf0d5b2c5b82d9.1664568492.git.quic_mathbern@quicinc.com>
| * Hexagon (target/hexagon) move store size tracking to translationTaylor Simpson2022-09-303-28/+41
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The store width is needed for packet commit, so it is stored in ctx->store_width. Currently, it is set when a store has a TCG override instead of a QEMU helper. In the QEMU helper case, the ctx->store_width is not set, we invoke a helper during packet commit that uses the runtime store width. This patch ensures ctx->store_width is set for all store instructions, so performance is improved because packet commit can generate the proper TCG store rather than the generic helper. We do this by - Use the attributes from the instructions during translation to set ctx->store_width - Remove setting of ctx->store_width from genptr.c Signed-off-by: Taylor Simpson <tsimpson@quicinc.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20220920080746.26791-3-tsimpson@quicinc.com>
| * Hexagon (target/hexagon) Change decision to set pkt_has_store_s[01]Taylor Simpson2022-09-304-10/+17
| | | | | | | | | | | | | | | | | | | | | | | | | | | | We have found cases where pkt_has_store_s[01] is set incorrectly. This leads to generating an unnecessary store that is left over from a previous packet. Add an attribute to determine if an instruction is a scalar store The attribute is attached to the fSTORE macro (hex_common.py) Update the logic in decode.c that sets pkt_has_store_s[01] Signed-off-by: Taylor Simpson <tsimpson@quicinc.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20220920080746.26791-4-tsimpson@quicinc.com>
| * Hexagon (target/hexagon) add instruction attributes from archlibTaylor Simpson2022-09-303-98/+133
| | | | | | | | | | | | | | | | | | | | The imported files from the architecture library have added some instruction attributes. Some of these will be used in a subsequent patch for determing the size of a store. Signed-off-by: Taylor Simpson <tsimpson@quicinc.com> Acked-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20220920080746.26791-2-tsimpson@quicinc.com>
* | accel/tcg: Introduce tb_pc and log_pcRichard Henderson2022-10-041-1/+1
| | | | | | | | | | | | | | | | | | | | | | The availability of tb->pc will shortly be conditional. Introduce accessor functions to minimize ifdefs. Pass around a known pc to places like tcg_gen_code, where the caller must already have the value. Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* | hw/core: Add CPUClass.get_pcRichard Henderson2022-10-041-0/+8
|/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Populate this new method for all targets. Always match the result that would be given by cpu_get_tb_cpu_state, as we will want these values to correspond in the logs. Reviewed-by: Taylor Simpson <tsimpson@quicinc.com> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> (target/sparc) Signed-off-by: Richard Henderson <richard.henderson@linaro.org> --- Cc: Eduardo Habkost <eduardo@habkost.net> (supporter:Machine core) Cc: Marcel Apfelbaum <marcel.apfelbaum@gmail.com> (supporter:Machine core) Cc: "Philippe Mathieu-Daudé" <f4bug@amsat.org> (reviewer:Machine core) Cc: Yanan Wang <wangyanan55@huawei.com> (reviewer:Machine core) Cc: Michael Rolnik <mrolnik@gmail.com> (maintainer:AVR TCG CPUs) Cc: "Edgar E. Iglesias" <edgar.iglesias@gmail.com> (maintainer:CRIS TCG CPUs) Cc: Taylor Simpson <tsimpson@quicinc.com> (supporter:Hexagon TCG CPUs) Cc: Song Gao <gaosong@loongson.cn> (maintainer:LoongArch TCG CPUs) Cc: Xiaojuan Yang <yangxiaojuan@loongson.cn> (maintainer:LoongArch TCG CPUs) Cc: Laurent Vivier <laurent@vivier.eu> (maintainer:M68K TCG CPUs) Cc: Jiaxun Yang <jiaxun.yang@flygoat.com> (reviewer:MIPS TCG CPUs) Cc: Aleksandar Rikalo <aleksandar.rikalo@syrmia.com> (reviewer:MIPS TCG CPUs) Cc: Chris Wulff <crwulff@gmail.com> (maintainer:NiosII TCG CPUs) Cc: Marek Vasut <marex@denx.de> (maintainer:NiosII TCG CPUs) Cc: Stafford Horne <shorne@gmail.com> (odd fixer:OpenRISC TCG CPUs) Cc: Yoshinori Sato <ysato@users.sourceforge.jp> (reviewer:RENESAS RX CPUs) Cc: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> (maintainer:SPARC TCG CPUs) Cc: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> (maintainer:TriCore TCG CPUs) Cc: Max Filippov <jcmvbkbc@gmail.com> (maintainer:Xtensa TCG CPUs) Cc: qemu-arm@nongnu.org (open list:ARM TCG CPUs) Cc: qemu-ppc@nongnu.org (open list:PowerPC TCG CPUs) Cc: qemu-riscv@nongnu.org (open list:RISC-V TCG CPUs) Cc: qemu-s390x@nongnu.org (open list:S390 TCG CPUs)
* Hexagon (target/hexagon) remove unused encodingsTaylor Simpson2022-09-191-23/+0Star
| | | | | | | | Remove encodings guarded by ifdef that is not defined Signed-off-by: Taylor Simpson <tsimpson@quicinc.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20220606222327.7682-4-tsimpson@quicinc.com>
* accel/tcg: Add pc and host_pc params to gen_intermediate_codeRichard Henderson2022-09-061-2/+4
| | | | | | | | | | | Pass these along to translator_loop -- pc may be used instead of tb->pc, and host_pc is currently unused. Adjust all targets at one time. Acked-by: Alistair Francis <alistair.francis@wdc.com> Acked-by: Ilya Leoshkevich <iii@linux.ibm.com> Tested-by: Ilya Leoshkevich <iii@linux.ibm.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* Hexagon (target/hexagon) make VyV operands use a unique tempTaylor Simpson2022-08-011-5/+4Star
| | | | | | | | | | | | | VyV operand is only used in the vshuff and vdeal instructions. These instructions write to both VyV and VxV operands. In the case where both operands are the same register, we need a separate location for VyV. We use the existing vtmp field in CPUHexagonState. Test case added in tests/tcg/hexagon/hvx_misc.c Signed-off-by: Taylor Simpson <tsimpson@quicinc.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20220718230320.24444-2-tsimpson@quicinc.com>
* Hexagon (target/hexagon) fix bug in mem_noshuf load exceptionTaylor Simpson2022-07-195-21/+59
| | | | | | | | | | | | | | | | | | | | | The semantics of a mem_noshuf packet are that the store effectively happens before the load. However, in cases where the load raises an exception, we cannot simply execute the store first. This change adds a probe to check that the load will not raise an exception before executing the store. If the load is predicated, this requires special handling. We check the condition before performing the probe. Since, we need the EA to perform the check, we move the GET_EA portion inside CHECK_NOSHUF_PRED. Test case added in tests/tcg/hexagon/mem_noshuf_exception.c Suggested-by: Alessandro Di Federico <ale@rev.ng> Suggested-by: Anton Johansson <anjo@rev.ng> Signed-off-by: Taylor Simpson <tsimpson@quicinc.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20220707210546.15985-3-tsimpson@quicinc.com>
* Hexagon (target/hexagon) fix store w/mem_noshuf & predicated loadTaylor Simpson2022-07-191-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Call the CHECK_NOSHUF macro multiple times: once in the fGEN_TCG_PRED_LOAD() and again in fLOAD(). Before this commit, a packet with a store and a predicated load with mem_noshuf that gets encoded like this: { P0 = cmp.eq(R17,#0x0) memw(R18+#0x0) = R2 if (!P0.new) R3 = memw(R17+#0x4) } ... would end up generating a branch over both the load and the store like so: ... brcond_i32 loc17,$0x0,eq,$L1 mov_i32 loc18,store_addr_1 qemu_st_i32 store_val32_1,store_addr_1,leul,0 qemu_ld_i32 loc16,loc7,leul,0 set_label $L1 ... Test cases added to tests/tcg/hexagon/mem_noshuf.c Co-authored-by: Taylor Simpson <tsimpson@quicinc.com> Signed-off-by: Brian Cain <bcain@quicinc.com> Signed-off-by: Taylor Simpson <tsimpson@quicinc.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20220707210546.15985-2-tsimpson@quicinc.com>
* Clean up decorations and whitespace around header guardsMarkus Armbruster2022-05-111-1/+1
| | | | | | | | Cleaned up with scripts/clean-header-guards.pl. Signed-off-by: Markus Armbruster <armbru@redhat.com> Message-Id: <20220506134911.2856099-5-armbru@redhat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
* Clean up header guards that don't match their file nameMarkus Armbruster2022-05-112-4/+4
| | | | | | | | | | | | | Header guard symbols should match their file name to make guard collisions less likely. Cleaned up with scripts/clean-header-guards.pl, followed by some renaming of new guard symbols picked by the script to better ones. Signed-off-by: Markus Armbruster <armbru@redhat.com> Message-Id: <20220506134911.2856099-2-armbru@redhat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> [Change to generated file ebpf/rss.bpf.skeleton.h backed out]
* compiler.h: replace QEMU_NORETURN with G_NORETURNMarc-André Lureau2022-04-211-4/+5
| | | | | | | | | | | | | G_NORETURN was introduced in glib 2.68, fallback to G_GNUC_NORETURN in glib-compat. Note that this attribute must be placed before the function declaration (bringing a bit of consistency in qemu codebase usage). Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com> Reviewed-by: Daniel P. Berrangé <berrange@redhat.com> Reviewed-by: Warner Losh <imp@bsdimp.com> Message-Id: <20220420132624.2439741-20-marcandre.lureau@redhat.com>
* exec/translator: Pass the locked filepointer to disas_log hookRichard Henderson2022-04-201-3/+4
| | | | | | | | | | We have fetched and locked the logfile in translator_loop. Pass the filepointer down to the disas_log hook so that it need not be fetched and locked again. Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20220417183019.755276-13-richard.henderson@linaro.org>
* target/hexagon: Remove qemu_set_log in hexagon_translate_initRichard Henderson2022-04-201-6/+0Star
| | | | | | | | | | This code appears to be trying to make sure there is a logfile. But that's already true -- the logfile will either be set by -D, or will be stderr. In either case, not appropriate here. Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20220417183019.755276-3-richard.henderson@linaro.org>
* Remove qemu-common.h include from most unitsMarc-André Lureau2022-04-061-1/+0Star
| | | | | | Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com> Message-Id: <20220323155743.1585078-33-marcandre.lureau@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
* target/hexagon: remove unused variableZongyuan Li2022-03-121-5/+1Star
| | | | | | | | | | | | | | When building with clang version 13.0.0 (eg. Fedora 13.0.0-3.fc35), two unused variables introduced by macro GATHER_FUNCTION and SCATTER_FUNCTION will cause building process failure due to [-Werror -Wunused-variable]. Signed-off-by: Zongyuan Li <zongyuan.li@smartx.com> Resolves: https://gitlab.com/qemu-project/qemu/-/issues/831 Message-Id: <20220124064339.56027-1-zongyuan.li@smartx.com> Reviewed-by: Thomas Huth <thuth@redhat.com> Reviewed-by: Taylor Simpson <tsimpson@quicinc.com> Signed-off-by: Taylor Simpson <tsimpson@quicinc.com>
* Hexagon (target/hexagon) assignment to c4 should wait until packet commitTaylor Simpson2022-03-121-5/+9
| | | | | | | | | | | | | On Hexagon, c4 is an alias for predicate registers P3:0. If we assign to c4 inside a packet with reads from predicate registers, the predicate reads should get the old values. Test case added to tests/tcg/hexagon/preg_alias.c Co-authored-by: Michael Lambert <mlambert@cuicinc.com> Signed-off-by: Taylor Simpson <tsimpson@quicinc.com> Message-Id: <20220210021556.9217-13-tsimpson@quicinc.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
* Hexagon (target/hexagon) fix bug in conv_df2uw_chopTaylor Simpson2022-03-121-1/+1
| | | | | | | | | | Fix typo that checked for 32 bit nan instead of 64 bit Test case added in tests/tcg/hexagon/usr.c Signed-off-by: Taylor Simpson <tsimpson@quicinc.com> Message-Id: <20220210021556.9217-11-tsimpson@quicinc.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
* Hexagon (target/hexagon) properly handle NaN in dfmin/dfmax/sfmin/sfmaxTaylor Simpson2022-03-121-10/+4Star
| | | | | | | | | | | | The float??_minnum implementation differs from Hexagon for SNaN, it returns NaN, but Hexagon returns the other input. So, we use float??_minimum_number. Test cases added to tests/tcg/hexagon/fpstuff.c Signed-off-by: Taylor Simpson <tsimpson@quicinc.com> Message-Id: <20220308190410.22355-1-tsimpson@quicinc.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
* Hexagon (target/hexagon) properly handle denorm in arch_sf_recip_commonTaylor Simpson2022-03-122-4/+8
| | | | | | | | | | | | | | | | The arch_sf_recip_common function was calling float32_getexp which adjusts for denorm, but the we actually need the raw exponent bits. This function is called from 3 instructions sfrecipa sffixupn sffixupd Test cases added to tests/tcg/hexagon/fpstuff.c Signed-off-by: Taylor Simpson <tsimpson@quicinc.com> Message-Id: <20220210021556.9217-6-tsimpson@quicinc.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
* Hexagon (target/hexagon) properly set FPINVF bit in sfcmp.uo and dfcmp.uoTaylor Simpson2022-03-121-4/+2Star
| | | | | | | | | | Instead of checking for nan arguments, use float??_unordered_quiet test cases added in a subsequent patch to more extensively test USR bits Signed-off-by: Taylor Simpson <tsimpson@quicinc.com> Message-Id: <20220210021556.9217-4-tsimpson@quicinc.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
* Hexagon HVX (target/hexagon) fix bug in HVX saturate instructionsTaylor Simpson2022-03-121-2/+2
| | | | | | | | | | Two tests added to tests/tcg/hexagon/hvx_misc.c v21.uw = vadd(v11.uw, v10.uw):sat v25:24.uw = vsub(v17:16.uw, v27:26.uw):sat Signed-off-by: Taylor Simpson <tsimpson@quicinc.com> Message-Id: <20220210021556.9217-3-tsimpson@quicinc.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
* Hexagon (target/hexagon) fix bug in circular addressingMichael Lambert2022-03-121-3/+3
| | | | | | | | | | | | Versions V3 and earlier should treat the "K_const" and "length" values as unsigned. Modified circ_test_v3() in tests/tcg/hexagon/circ.c to reproduce the bug Signed-off-by: Michael Lambert <mlambert@quicinc.com> Signed-off-by: Taylor Simpson <tsimpson@quicinc.com> Message-Id: <20220210021556.9217-2-tsimpson@quicinc.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
* target: Use ArchCPU as interface to target CPUPhilippe Mathieu-Daudé2022-03-061-1/+1
| | | | | | | | | | ArchCPU is our interface with target-specific code. Use it as a forward-declared opaque pointer (abstract type), having its structure defined by each target. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20220214183144.27402-15-f4bug@amsat.org>
* target: Introduce and use OBJECT_DECLARE_CPU_TYPE() macroPhilippe Mathieu-Daudé2022-03-061-3/+3
| | | | | | | | | Replace the boilerplate code to declare CPU QOM types and macros, and forward-declare the CPU instance type. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20220214183144.27402-14-f4bug@amsat.org>
* target: Use CPUArchState as interface to target-specific CPU statePhilippe Mathieu-Daudé2022-03-061-6/+2Star
| | | | | | | | | | While CPUState is our interface with generic code, CPUArchState is our interface with target-specific code. Use CPUArchState as an abstract type, defined by each target. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20220214183144.27402-13-f4bug@amsat.org>
* target/hexagon: Add missing 'hw/core/cpu.h' includePhilippe Mathieu-Daudé2022-03-061-0/+1
| | | | | | | | | | HexagonCPU field parent_class is of type CPUClass, which is declared in "hw/core/cpu.h". Reviewed-by: Damien Hedde <damien.hedde@greensocs.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20220214183144.27402-11-f4bug@amsat.org>
* Hexagon (target/hexagon) convert to OBJECT_DECLARE_TYPETaylor Simpson2022-03-061-7/+3Star
| | | | | | | | | | Suggested-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Taylor Simpson <tsimpson@quicinc.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20220211033034.21107-1-tsimpson@quicinc.com> [PMD: Add missing "qom/object.h" include] Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
* exec/exec-all: Move 'qemu/log.h' include in units requiring itPhilippe Mathieu-Daudé2022-02-212-0/+3
| | | | | | | | | | | | | Many files use "qemu/log.h" declarations but neglect to include it (they inherit it via "exec/exec-all.h"). "exec/exec-all.h" is a core component and shouldn't be used that way. Move the "qemu/log.h" inclusion locally to each unit requiring it. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Acked-by: Thomas Huth <thuth@redhat.com> Message-Id: <20220207082756.82600-10-f4bug@amsat.org> Signed-off-by: Thomas Huth <thuth@redhat.com>
* target/hexagon/cpu.h: don't include qemu-common.hPeter Maydell2021-12-151-1/+0Star
| | | | | | | | | | | | | | | The qemu-common.h header is not supposed to be included from any other header files, only from .c files (as documented in a comment at the start of it). Move the include to linux-user/hexagon/cpu_loop.c, which needs it for the declaration of cpu_exec_step_atomic(). Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Taylor Simpson <tsimpson@quicinc.com> Message-id: 20211129200510.1233037-3-peter.maydell@linaro.org
* Merge remote-tracking branch 'remotes/quic/tags/pull-hex-20211103' into stagingRichard Henderson2021-11-0438-47/+7557
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This series adds support for the Hexagon Vector eXtensions (HVX) These instructions are documented here https://developer.qualcomm.com/downloads/qualcomm-hexagon-v66-hvx-programmer-s-reference-manual Hexagon HVX is a wide vector engine with 128 byte vectors. See patch 01 Hexagon HVX README for more information. *** Changes in v2 *** Remove HVX tests from makefile to avoid need for toolchain upgrade # gpg: Signature made Wed 03 Nov 2021 05:14:44 PM EDT # gpg: using RSA key 7B0244FB12DE4422 # gpg: Good signature from "Taylor Simpson (Rock on) <tsimpson@quicinc.com>" [marginal] # gpg: WARNING: This key is not certified with sufficiently trusted signatures! # gpg: It is not certain that the signature belongs to the owner. # Primary key fingerprint: 3635 C788 CE62 B91F D4C5 9AB4 7B02 44FB 12DE 4422 * remotes/quic/tags/pull-hex-20211103: (30 commits) Hexagon HVX (tests/tcg/hexagon) histogram test Hexagon HVX (tests/tcg/hexagon) scatter_gather test Hexagon HVX (tests/tcg/hexagon) hvx_misc test Hexagon HVX (tests/tcg/hexagon) vector_add_int test Hexagon HVX (target/hexagon) import instruction encodings Hexagon HVX (target/hexagon) instruction decoding Hexagon HVX (target/hexagon) import semantics Hexagon HVX (target/hexagon) helper overrides - vector stores Hexagon HVX (target/hexagon) helper overrides - vector loads Hexagon HVX (target/hexagon) helper overrides - vector splat and abs Hexagon HVX (target/hexagon) helper overrides - vector compares Hexagon HVX (target/hexagon) helper overrides - vector logical ops Hexagon HVX (target/hexagon) helper overrides - vector max/min Hexagon HVX (target/hexagon) helper overrides - vector shifts Hexagon HVX (target/hexagon) helper overrides - vector add & sub Hexagon HVX (target/hexagon) helper overrides - vector assign & cmov Hexagon HVX (target/hexagon) helper overrides for histogram instructions Hexagon HVX (target/hexagon) helper overrides infrastructure Hexagon HVX (target/hexagon) TCG generation Hexagon HVX (target/hexagon) helper functions ... Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
| * Hexagon HVX (target/hexagon) import instruction encodingsTaylor Simpson2021-11-034-0/+819
| | | | | | | | | | Acked-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Taylor Simpson <tsimpson@quicinc.com>
| * Hexagon HVX (target/hexagon) instruction decodingTaylor Simpson2021-11-034-2/+283
| | | | | | | | | | | | | | Add new file to target/hexagon/meson.build Acked-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Taylor Simpson <tsimpson@quicinc.com>
| * Hexagon HVX (target/hexagon) import semanticsTaylor Simpson2021-11-034-0/+2804
| | | | | | | | | | | | | | | | | | | | | | Imported from the Hexagon architecture library imported/allext.idef Top level file for all extensions imported/mmvec/ext.idef HVX instruction definitions Support functions added to target/hexagon/genptr.c Acked-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Taylor Simpson <tsimpson@quicinc.com>
| * Hexagon HVX (target/hexagon) helper overrides - vector storesTaylor Simpson2021-11-031-0/+218
| | | | | | | | | | Acked-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Taylor Simpson <tsimpson@quicinc.com>
| * Hexagon HVX (target/hexagon) helper overrides - vector loadsTaylor Simpson2021-11-031-0/+150
| | | | | | | | | | Acked-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Taylor Simpson <tsimpson@quicinc.com>
| * Hexagon HVX (target/hexagon) helper overrides - vector splat and absTaylor Simpson2021-11-031-0/+26
| | | | | | | | | | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Taylor Simpson <tsimpson@quicinc.com>
| * Hexagon HVX (target/hexagon) helper overrides - vector comparesTaylor Simpson2021-11-031-0/+103
| | | | | | | | | | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Taylor Simpson <tsimpson@quicinc.com>
| * Hexagon HVX (target/hexagon) helper overrides - vector logical opsTaylor Simpson2021-11-031-0/+42
| | | | | | | | | | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Taylor Simpson <tsimpson@quicinc.com>
| * Hexagon HVX (target/hexagon) helper overrides - vector max/minTaylor Simpson2021-11-031-0/+34
| | | | | | | | | | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Taylor Simpson <tsimpson@quicinc.com>
| * Hexagon HVX (target/hexagon) helper overrides - vector shiftsTaylor Simpson2021-11-031-0/+122
| | | | | | | | | | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Taylor Simpson <tsimpson@quicinc.com>
| * Hexagon HVX (target/hexagon) helper overrides - vector add & subTaylor Simpson2021-11-031-0/+50
| | | | | | | | | | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Taylor Simpson <tsimpson@quicinc.com>
| * Hexagon HVX (target/hexagon) helper overrides - vector assign & cmovTaylor Simpson2021-11-031-0/+31
| | | | | | | | | | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Taylor Simpson <tsimpson@quicinc.com>
| * Hexagon HVX (target/hexagon) helper overrides for histogram instructionsTaylor Simpson2021-11-031-0/+106
| | | | | | | | | | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Taylor Simpson <tsimpson@quicinc.com>
| * Hexagon HVX (target/hexagon) helper overrides infrastructureTaylor Simpson2021-11-036-9/+35
| | | | | | | | | | | | | | | | | | | | Build the infrastructure to create overrides for HVX instructions. We create a new empty file (gen_tcg_hvx.h) that will be populated in subsequent patches. Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Taylor Simpson <tsimpson@quicinc.com>
| * Hexagon HVX (target/hexagon) TCG generationTaylor Simpson2021-11-033-4/+311
| | | | | | | | | | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Taylor Simpson <tsimpson@quicinc.com>
generated by cgit v1.2.3-55-g7522 (git 2.39.0) at 2024-11-21 17:38:59 +0100