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path: root/target/i386/translate.c
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* target/i386: Implement CPUID_EXT_RDRANDRichard Henderson2019-05-221-15/+47
* tcg: Hoist max_insns computation to tb_gen_codeRichard Henderson2019-04-241-2/+2
* target/i386: Generate #UD for LOCK on a register incrementPeter Maydell2019-04-091-0/+5
* avoid TABs in files that only contain a fewPaolo Bonzini2019-01-111-6/+6
* target/i386: Generate #UD when applying LOCK to a register destinationRichard Henderson2018-11-271-15/+20
* target/i386: Remove #ifdeffed-out icebp debugging hackPeter Maydell2018-10-311-6/+0Star
* target/i386: fix translation for icount modePavel Dovgalyuk2018-10-021-3/+3
* target/i386: rename HF_SVMI_MASK to HF_GUEST_MASKPaolo Bonzini2018-10-021-2/+2
* target/i386: move x86_64_hregs to DisasContextEmilio G. Cota2018-10-021-153/+154
* target/i386: move cpu_tmp1_i64 to DisasContextEmilio G. Cota2018-10-021-80/+80
* target/i386: move cpu_tmp3_i32 to DisasContextEmilio G. Cota2018-10-021-32/+32
* target/i386: move cpu_tmp2_i32 to DisasContextEmilio G. Cota2018-10-021-173/+174
* target/i386: move cpu_ptr1 to DisasContextEmilio G. Cota2018-10-021-26/+26
* target/i386: move cpu_ptr0 to DisasContextEmilio G. Cota2018-10-021-49/+52
* target/i386: move cpu_tmp4 to DisasContextEmilio G. Cota2018-10-021-39/+39
* target/i386: move cpu_tmp0 to DisasContextEmilio G. Cota2018-10-021-138/+144
* target/i386: move cpu_T1 to DisasContextEmilio G. Cota2018-10-021-171/+170Star
* target/i386: move cpu_T0 to DisasContextEmilio G. Cota2018-10-021-580/+594
* target/i386: move cpu_A0 to DisasContextEmilio G. Cota2018-10-021-236/+236
* target/i386: move cpu_cc_srcT to DisasContextEmilio G. Cota2018-10-021-14/+18
* fix "Missing break in switch" coverity reportsPaolo Bonzini2018-08-231-0/+2
* target-i386: Allow interrupt injection after STGIJan Kiszka2018-06-281-1/+2
* target/i386: Fix BLSR and BLSIRichard Henderson2018-06-281-17/+9Star
* tcg: Pass tb and index to tcg_gen_exit_tb separatelyRichard Henderson2018-06-021-4/+4
* tcg: fix s/compliment/complement/ typosEmilio G. Cota2018-05-201-1/+1
* translator: merge max_insns into DisasContextBaseEmilio G. Cota2018-05-091-4/+1Star
* Add missing bit for SSE instr in VEX decodingEugene Minibaev2018-04-091-1/+3
* target/i386: Fix andn instructionAlexandro Sanchez Bach2018-04-051-1/+1
* tcg: Remove TCGV_UNUSED* and TCGV_IS_UNUSED*Richard Henderson2017-12-291-7/+6Star
* target/i386: Fix handling of VEX prefixesPeter Maydell2017-12-211-1/+1
* target/i386: Fix compiler warningsStefan Weil2017-12-211-3/+4
* Merge remote-tracking branch 'remotes/rth/tags/pull-dis-20171026' into stagingPeter Maydell2017-10-271-7/+1Star
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| * disas: Remove unused flags argumentsRichard Henderson2017-10-251-1/+1
| * target/i386: Convert to disas_set_info hookRichard Henderson2017-10-251-7/+1Star
* | tcg: Initialize cpu_env genericallyRichard Henderson2017-10-241-3/+0Star
* | tcg: define tcg_init_ctx and make tcg_ctx a pointerEmilio G. Cota2017-10-241-1/+1
* | target/i386: check CF_PARALLEL instead of parallel_cpusEmilio G. Cota2017-10-241-2/+2
* | tcg: convert tb->cflags reads to tb_cflags(tb)Emilio G. Cota2017-10-241-24/+24
* | qom: Introduce CPUClass.tcg_initializeRichard Henderson2017-10-241-6/+0Star
* | tcg: Remove TCGV_EQUAL*Richard Henderson2017-10-241-3/+3
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* target/i386: trap on instructions longer than >15 bytesPaolo Bonzini2017-10-161-7/+22
* target/i386: introduce x86_ld*_codePaolo Bonzini2017-10-161-103/+125
* tcg: remove addr argument from lookup_tb_ptrEmilio G. Cota2017-10-101-12/+5Star
* x86: Correct translation of some rdgsbase and wrgsbase encodingsTodd Eisenberger2017-10-101-2/+2
* target/i386: set rip_offset for further SSE instructionsJoseph Myers2017-09-191-1/+2
* target/i386: [tcg] Port to generic translation frameworkLluís Vilanova2017-09-061-87/+19Star
* target/i386: [tcg] Port to disas_logLluís Vilanova2017-09-061-13/+19
* target/i386: [tcg] Port to tb_stopLluís Vilanova2017-09-061-12/+14
* target/i386: [tcg] Port to translate_insnLluís Vilanova2017-09-061-24/+42
* target/i386: [tcg] Port to breakpoint_checkLluís Vilanova2017-09-061-12/+34
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